Wellein G, Zeiser T, Hager G, Donath S (2006)
Publication Language: English
Publication Type: Journal article, Original article
Publication year: 2006
Publisher: Elsevier
Book Volume: 35
Pages Range: 910-919
Journal Issue: 8-9: Proceedings of the First International Conference for Mesoscopic Methods in Engineering and Science
DOI: 10.1016/j.compfluid.2005.02.008
This report presents a comprehensive survey of the effect of different data layouts on the single processor performance characteristics for the lattice Boltzmann method both for commodity "off-the-shelf" (COTS) architectures and tailored HPC systems, such as vector computers. We cover modern 64-bit processors ranging from IA32 compatible (Intel Xeon/Nocona, AMD Opteron), superscalar RISC (IBM Power4), IA64 (Intel Itanium 2) to classical vector (NEC SX6+) and novel vector (Cray X1) architectures. Combining different data layouts with architecture dependent optimization strategies we demonstrate that the optimal implementation strongly depends on the architecture used. In particular, the correct choice of the data layout could supersede complex cache-blocking techniques in our kernels. Furthermore our results demonstrate that vector systems can outperform COTS architectures by one order of magnitude. © 2005 Elsevier Ltd. All rights reserved.
APA:
Wellein, G., Zeiser, T., Hager, G., & Donath, S. (2006). On the single processor performance of simple lattice Boltzmann kernels. Computers & Fluids, 35(8-9: Proceedings of the First International Conference for Mesoscopic Methods in Engineering and Science), 910-919. https://dx.doi.org/10.1016/j.compfluid.2005.02.008
MLA:
Wellein, Gerhard, et al. "On the single processor performance of simple lattice Boltzmann kernels." Computers & Fluids 35.8-9: Proceedings of the First International Conference for Mesoscopic Methods in Engineering and Science (2006): 910-919.
BibTeX: Download