An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors

Conference contribution


Publication Details

Author(s): Hofmann J, Hager G, Wellein G, Fey D
Publisher: Springer
Publishing place: Cham
Publication year: 2017
Title of series: Lecture Notes in Computer Science
Conference Proceedings Title: High Performance Computing. ISC 2017. Lecture Notes in Computer Science, vol 10266
ISBN: 978-3-319-58667-0


FAU Authors / FAU Editors

Fey, Dietmar Prof. Dr.-Ing.
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Hager, Georg Dr.
Regionales Rechenzentrum Erlangen (RRZE)
Hofmann, Johannes
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Wellein, Gerhard Prof. Dr.
Professur für Höchstleistungsrechnen


How to cite

APA:
Hofmann, J., Hager, G., Wellein, G., & Fey, D. (2017). An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors. In High Performance Computing. ISC 2017. Lecture Notes in Computer Science, vol 10266. Frankfurt: Cham: Springer.

MLA:
Hofmann, Johannes, et al. "An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors." Proceedings of the 32nd International Conference on High Performance Computing: ISC High Performance 2017, Frankfurt Cham: Springer, 2017.

BibTeX: 

Last updated on 2018-07-12 at 13:50