Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution

Unveröffentlicht / Preprint

Details zur Publikation

Autor(en): Schmitt C, Schmid M, Kuckuk S, Köstler H, Teich J, Hannig F
Titel Sammelwerk: Parallel Processing Letters
Verlag: World Scientific
Jahr der Veröffentlichung: 2018
Band: 28
Heftnummer: 4


Not only in the field of high-performance computing, field-programmable gate arrays (FPGAs) are a soaringly popular accelerator technology. However, they use a completely different programming paradigm and tool set compared to CPUs or even GPUs, adding extra development steps and requiring special knowledge, hindering widespread use in scientific computing. To bridge this programmability gap, domain-specific languages are a popular choice to generate low-level implementations from an abstract algorithm description. In this work, we demonstrate our approach for the generation of numerical solver implementations based on the multigrid method for FPGAs from the same code base that is also used to generate code for CPUs using a hybrid parallelization of MPI and OpenMP. Our approach yields in a hardware design that can compute up to 11 V-cycles per second with an input grid size of 4096x4096 and solution on the coarsest using the conjugate gradient method on a mid-range FPGA, beating vectorized, multi-threaded execution on an Intel Xeon processor.

FAU-Autoren / FAU-Herausgeber

Hannig, Frank PD Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Köstler, Harald PD Dr.
Lehrstuhl für Informatik 10 (Systemsimulation)
Kuckuk, Sebastian
Lehrstuhl für Informatik 10 (Systemsimulation)
Schmid, Moritz
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Schmitt, Christian
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Zuletzt aktualisiert 2018-06-12 um 15:53