Evaluation of state-of-the-art hardware architectures for fast cone-beam CT reconstruction

Beitrag in einer Fachzeitschrift
(Originalarbeit)


Details zur Publikation

Autor(en): Scherl H, Kowarschik M, Hofmann H, Keck B, Hornegger J
Zeitschrift: Parallel Computing
Verlag: Elsevier
Jahr der Veröffentlichung: 2012
Band: 38
Heftnummer: 3
Seitenbereich: 111-124
ISSN: 0167-8191


Abstract


We present an evaluation of state-of-the-art computer hardware architectures for implementing the FDK method, which solves the 3-D image reconstruction task in cone-beam computed tomography (CT). The computational complexity of the FDK method prohibits its use for many clinical applications unless appropriate hardware acceleration is employed. Today's most powerful hardware architectures for high-performance computing applications are based on standard multi-core processors, off-the-shelf graphics boards, the Cell Broadband Engine Architecture (CBEA), or customized accelerator platforms (e.g., FPGA-based computer components). For each hardware platform under consideration, we describe a thoroughly optimized implementation of the most time-consuming parts of the FDK algorithm; the filtering step as well as the subsequent back-projection step. We further explain the required code transformations to parallelize the algorithm for the respective target architecture. We compare both the implementation complexity and the resulting performance of all architectures under consideration using the same two medical datasets which have been acquired using a standard C-arm device. Our optimized back-projection implementations achieve at least a speedup of 6.5 (CBEA, two processors), 22.0 (GPU, single board), and 35.8 (FPGA, 9 chips) compared to a standard workstation equipped with a quad-core processor. © 2011 Elsevier B.V. All rights reserved.



FAU-Autoren / FAU-Herausgeber

Hofmann, Hannes
Lehrstuhl für Informatik 5 (Mustererkennung)
Hornegger, Joachim Prof. Dr.-Ing.
Lehrstuhl für Informatik 5 (Mustererkennung)
Keck, Benjamin
Lehrstuhl für Informatik 5 (Mustererkennung)


Autor(en) der externen Einrichtung(en)
Siemens AG


Zitierweisen

APA:
Scherl, H., Kowarschik, M., Hofmann, H., Keck, B., & Hornegger, J. (2012). Evaluation of state-of-the-art hardware architectures for fast cone-beam CT reconstruction. Parallel Computing, 38(3), 111-124. https://dx.doi.org/10.1016/j.parco.2011.10.004

MLA:
Scherl, Holger, et al. "Evaluation of state-of-the-art hardware architectures for fast cone-beam CT reconstruction." Parallel Computing 38.3 (2012): 111-124.

BibTeX: 

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