Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor

Conference contribution


Publication Details

Author(s): Salcic Z, Nadeem M, Park H, Teich J
Publication year: 2016
Conference Proceedings Title: Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16)
Pages range: 233-240


FAU Authors / FAU Editors

Park, Heejong Dr.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Teich, Jürgen Prof. Dr.-Ing.
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


How to cite

APA:
Salcic, Z., Nadeem, M., Park, H., & Teich, J. (2016). Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) (pp. 233-240). Lyon, FR.

MLA:
Salcic, Zoran, et al. "Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor." Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), Lyon 2016. 233-240.

BibTeX: 

Last updated on 2018-19-04 at 03:37