ReCoNet: Modeling and implementation of fault tolerant distributed reconfigurable hardware
Haubelt C, Koch D, Teich J (2003)
Publication Status: Published
Publication Type: Conference contribution, Conference Contribution
Publication year: 2003
Publisher: Institute of Electrical and Electronics Engineers Inc.
Pages Range: 343-348
Article Number: 1232851
Conference Proceedings Title: Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI2003)
Event location: São Paulo
ISBN: 9780769520094
DOI: 10.1109/SBCCI.2003.1232851
Abstract
Recent research was mainly focused on the OS support for a single reconfigurable chip. This paper presents a general approach to manage fault tolerant distributed reconfigurable hardware. In order to run such a system, three basic tasks must be implemented: (i) rerouting to compensate line errors, (ii) rebinding to compensate node failures, and (iii) hardware reconfiguration to allow the optimization of these systems during runtime. This paper proposes first ideas and solutions of these management functions. Furthermore, a prototype implementation consisting of four fully connected FPGAs is presented.
Authors with CRIS profile
Christian Haubelt
Technische Fakultät
Jürgen Teich
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Related research project(s)
How to cite
APA:
Haubelt, C., Koch, D., & Teich, J. (2003). ReCoNet: Modeling and implementation of fault tolerant distributed reconfigurable hardware. In Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI2003) (pp. 343-348). São Paulo, BR: Institute of Electrical and Electronics Engineers Inc..
MLA:
Haubelt, Christian, Dirk Koch, and Jürgen Teich. "ReCoNet: Modeling and implementation of fault tolerant distributed reconfigurable hardware." Proceedings of the 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003, São Paulo Institute of Electrical and Electronics Engineers Inc., 2003. 343-348.
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