A flexible mixed-signal image processing pipeline using 3D chip stacks
Shi L, Söll C, Pfundt B, Bänisch A, Reichenbach M, Seiler J, Ussmueller T, Weigel R (2016)
Publication Status: Published
Publication Type: Journal article, Original article
Publication year: 2016
Journal
Publisher: Springer Verlag (Germany)
Book Volume: 14
Pages Range: 517-534
Journal Issue: 3
DOI: 10.1007/s11554-016-0628-5
Abstract
This work presents a highly flexible mixed-signal CMOS image sensor suitable for smart camera applications. These systems need to fit different constraints regarding power consumption, speed and quality, and the optimal compromise may differ depending on the application. Moreover, the best implementation of a desired image processing task may be in the analog or the digital domain, or even a combined computation. Different aspects starting from the image sensor and signal acquisition up to the pre-processing in analog and digital domain are investigated in this paper to optimize not just one part of the system, but the whole system altogether. Moreover, it is shown that analog processing algorithms can improve signal quality, processing speed and latency while being able to save power, which is important for real-time systems. In order to be able to carry out spatial operations, the state-of-the-art sensor is modified to be able to read out multiple pixels at the same time. This allows analog spatial filter operations which consume significantly less power. As an example, an averaging filter is described which needs less than 5.3 % of the power–time product of a digital implementation for one computation. To enhance data throughput and flexibility, 3D chip stacking is proposed to partition the sensor in smaller units and enable massively parallel processing.
Authors with CRIS profile
Lan Shi
Lehrstuhl für Technische Elektronik
Christopher Söll
Lehrstuhl für Technische Elektronik
Benjamin Pfundt
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Andreas Bänisch
Lehrstuhl für Technische Elektronik
Marc Reichenbach
Lehrstuhl für Informatik 3 (Rechnerarchitektur)
Jürgen Seiler
Lehrstuhl für Multimediakommunikation und Signalverarbeitung
Robert Weigel
Lehrstuhl für Technische Elektronik
Involved external institutions
Austria (AT)How to cite
APA:
Shi, L., Söll, C., Pfundt, B., Bänisch, A., Reichenbach, M., Seiler, J.,... Weigel, R. (2016). A flexible mixed-signal image processing pipeline using 3D chip stacks. Journal of Real-Time Image Processing, 14(3), 517-534. https://dx.doi.org/10.1007/s11554-016-0628-5
MLA:
Shi, Lan, et al. "A flexible mixed-signal image processing pipeline using 3D chip stacks." Journal of Real-Time Image Processing 14.3 (2016): 517-534.
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