DFG SFB/Transregio 89 "Invasive Computing"

Third Party Funds Group - Overall project


Project Details

Project leader:
Prof. Dr.-Ing. Jürgen Teich

Project members:
Vahid Lari
Srinivas Boppu
Dr.-Ing. Alexandru-Petru Tanase
Dr.-Ing. Jürgen Kleinöder
Dr.-Ing. Stefan Wildermann
Marcel Brand
Prof. Dr.-Ing. Felix Freiling
Prof. Dr.-Ing. Michael Glaß
Christian Heidorn
Prof. Dr.-Ing. Wolfgang Schröder-Preikschat
Tobias Schwarzer
PD Dr.-Ing. Frank Hannig
Behnaz Pourmohseni
Dr. Sandra Mattauch
Michael Witterauf
Stefanie Kugler
Prof. Dr.-Ing. Jürgen Teich
Sascha Roloff

Contributing FAU Organisations:
Juniorprofessur für Informatik
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Lehrstuhl für Informatik 1 (IT-Sicherheitsinfrastrukturen)
Lehrstuhl für Informatik 4 (Verteilte Systeme und Betriebssysteme)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen

Funding source: DFG / Sonderforschungsbereich / Transregio (SFB / TRR) (Deutsche Forschungsgemeinschaft (DFG))
Acronym: TRR 89
Start date: 01/07/2010
End date: 30/06/2022


Abstract (technical / expert description):

Invasive computing denotes a novel paradigm for the design and programming of future parallel computing systems. Its unique characteristic is to give a programmer explicit handles to specify and argue about resource requirements desired, or required in different phases of execution: Using an invade command, an application may instruct the operating system to claim a set of processor, memory and communication resources for being allocated for a -by default- subsequent exclusive use. In an infect phase, the application workload is then spread and executed on the obtained claim of resources. A retreat command finally frees a claim again and the application may resume sequential execution. To support this idea of self-adaptive and resource-aware programming, not only novel programming concepts, languages, compilers and operating system concepts had to be developed from scratch, but also revolutionary architectural changes in the design of MPSoCs (multiprocessor system-on-a-chip) including mechanisms to allocate and isolate resources on demand.
Mission I: Basic Principles and Invasive Efficiency. As major results of the first funding phase, substantial gains in multicore utilisation and efficiency have been shown to be achievable by only claiming resources when necessary and retreating from them if not needed.
Mission II: *-Predictability. A unique jewel of invasive computing is the inherent capability to isolate even distributed applications from each other by not sharing resources. This feature has shown to enable *-predictability of non-functional qualities of program execution such as execution time, throughput, but also safety and security properties. Using current multicore platforms and operating systems, little if no support for hardware and/or temporal isolation can be established on demand of an application program. By exploiting the fact that resources may be (temporally) claimed exclusively, we were able to show that *-predictability may be enabled on program demand using invasive computing which uses run-to-completion as the default mode of thread execution, partial virtualisation and techniques for memory reconfiguration and bandwidth guarantees on the designed invasible NoC.
Mission III: Beating Run-Time Uncertainties and Run-Time Requirement Enforcement. Not only the interferences caused when sharing resources such as caches, processors and communication links as being the practice today, makes the analysis of non-functional properties hard. The bounds themselves or their variability might be much too large for any practical use. Unfortunately, isolation alone does not help to reduce the remaining uncertainty caused by input (problem size), environment (e.g. temperature), and machine state (e.g., cache, power manager, etc.). Our goal of phase III is therefore to close this missing link for making multicore systems available to be used for the billion dollar market of embedded and cyber-physical IoT products where application programs require the strict or at least loose enforcement of tight non-functional property ranges. Here, through the static analysis of robustness and the automatic generation of verifiable run-time requirement enforcer (RRE) modules (additional code that either locally or globally observes and controls the satisfaction of requirements within prescribed corridors) in combination with run-time requirement monitoring (RRM), we expect to provide the missing link to successfully combine resource awareness and tight predictability of non-functional aspects of program execution on multicore platforms.

Sub projects:

Invasive Tightly-Coupled Processor Arrays (B02)
Validation and Demonstrator (Z02)
Simulation of Invasive Applications and Invasive Architectures (C02)
Simulative Design Space Exploration (C02)
Invasive Run-Time Support System (iRTSS) (C01)
Security in Invasive Computing Systems
Compilation and Code Generation for Invasive Programs (C03)
Design-Time Characterisation and Analysis of Invasive Algorithmic Patterns (A04)
Integration and Coupling of Tightly Coupled Processor Arrays (T01)
Autonomous, Self-Optimising Communication Infrastructures for MPSoCs (B05)
Central Services of the Transregional Collaborative Research Centre and Public Relations (Z01)
Basics of Invasive Computing (A01)
Security in Invasive Computing Systems (C05)


External Partners

Karlsruhe Institute of Technology (KIT)
Technische Universität München (TUM)


Publications
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Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2017). A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays. Cancun, Mexico, MX.
Brand, M., Hannig, F., Tanase, A.-P., & Teich, J. (2017, July). Efficiency in ILP Processing by Using Orthogonality. Poster presentation at The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017), Seattle, US.
Brand, M., Hannig, F., Tanase, A.-P., & Teich, J. (2017). Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. In 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (pp. 5-12). Korea University, Seoul, Korea, KR.
Khdr, H., Pagani, S., Rodrigues Sousa, E., Lari, V., Pathania, A., Hannig, F.,... Henkel, J. (2017). Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Transactions on Computers, 66(3), 488--501. https://dx.doi.org/10.1109/TC.2016.2595560
Pourmohseni, B., Wildermann, S., Glaß, M., & Teich, J. (2017). Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems. Grenoble, FR.
Sousa, É., Chakraborty, A., Tanase, A.-P., Hannig, F., & Teich, J. (2017). TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays. Poster presentation at Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, MX.
Teich, J., Glaß, M., Roloff, S., Schröder-Preikschat, W., Snelting, G., Weichslgartner, A., & Wildermann, S. (2016). Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution using Invasive Computing. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) (pp. 313-320). Lyon, FR.
Roloff, S., Schafhauser, D., Hannig, F., & Teich, J. (2015). Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) (pp. 44:1-44:6). San Francisco, CA, US: Institute of Electrical and Electronics Engineers Inc..
Hannig, F., Lari, V., Boppu, S., Tanase, A.-P., & Reiche, O. (2014). Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Transactions on Embedded Computing Systems, 13(4s), 133:1-133:29. https://dx.doi.org/10.1145/2584660
Teich, J., Henkel, J., Herkersdorf, A., Schmitt-Landsiedel, D., Schröder-Preikschat, W., & Snelting, G. (2011). Invasive Computing: An Overview. In M. Hübner and J. Becker (Eds.), Multiprocessor System-on-Chip - Hardware Design and Tool Integration (pp. 241-268). New York: Springer.

Last updated on 2018-20-09 at 09:34