TRR 89: Invasive Computing

Third Party Funds Group - Overall project


Project Details

Project leader:
Prof. Dr.-Ing. Jürgen Teich

Project members:
Sascha Roloff
Prof. Dr.-Ing. Felix Freiling
Prof. Dr.-Ing. Wolfgang Schröder-Preikschat
Dr.-Ing. Jürgen Kleinöder
Dr.-Ing. Stefan Wildermann
Dr.-Ing. Frank Hannig
Tobias Schwarzer
Behnaz Pourmohseni
Prof. Dr.-Ing. Jürgen Teich
Marcel Brand
Michael Witterauf
Dr. Sandra Mattauch
Stefanie Kugler

Contributing FAU Organisations:
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Lehrstuhl für Informatik 4 (Verteilte Systeme und Betriebssysteme)
Lehrstuhl für Informatik 1 (IT-Sicherheitsinfrastrukturen)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen

Funding source: DFG / Sonderforschungsbereich / Transregio (SFB / TRR)
Acronym: TRR 89
Start date: 01/07/2010
End date: 30/06/2018


Abstract (technical / expert description):


The main idea and novelty of invasive computing is to introduce resource-aware programming support in the sense that a given program gets the ability to explore and dynamically spread its computations to processors similar to a phase of invasion, then to execute portions of code of high parallelism degree in parallel based on the available (invasible) region on a given multi-processor architecture. Afterwards, once the program terminates or if the degree of parallelism should be lower again, the program may enter a retreat phase, deallocate resources and resume execution again, for example, sequentially on a single processor. To support this idea of self-adaptive and resource-aware programming new programming concepts, languages, compilers and operating systems are necessary as well as architectural changes in the design of MPSoCs (Multi-Processor Systems-on-a-Chip) to efficiently support invasion, infection and retreat operations by involving concepts for dynamic processor, interconnect and memory reconfiguration. Decreasing feature sizes have also led to a rethinking in the design of multi-million transistor system-on-chip (SoC) architectures, envisioning dramatically increasing rates of temporary and permanent faults and feature variations.



As we can foresee SoCs with 1000 or more processors on a single chip in the year 2020, static and central management concepts to control the execution of all resources might have met their limits long before and are therefore not appropriate. Invasion might provide the required self-organising behaviour to conventional programs for being able to provide scalability, higher resource utilisation, required fault tolerance, and of course also performance gains by adjusting the amount of allocated resources to the temporal needs of a running application. This thought opens a new way of thinking about parallel algorithm design. Based on algorithms utilising invasion and negotiating resources with others, we can imagine that corresponding programs become personalised objects, competing with other applications running simultaneously on an MPSoC.


Sub projects:

Simulative Design Space Exploration (C02)
Validation and Demonstrator (Z02)
Design-Time Characterisation and Analysis of Invasive Algorithmic Patterns (A04)
Autonomous, Self-Optimising Communication Infrastructures for MPSoCs (B05)
Compilation and Code Generation for Invasive Programs (C03)
Invasive Tightly-Coupled Processor Arrays (B02)
Invasive Run-Time Support System (iRTSS) (C01)
Simulation of Invasive Applications and Invasive Architectures (C02)
Basics of Invasive Computing (A01)
Central Services of the Transregional Collaborative Research Centre and Public Relations (Z01)
Integration and Coupling of Tightly Coupled Processor Arrays (T01)


External Partners

Technische Universität München (TUM)
Karlsruhe Institute of Technology (KIT)


Publications

Pourmohseni, B., Wildermann, S., Glaß, M., & Teich, J. (2017). Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems. Grenoble, FR.
Teich, J., Glaß, M., Roloff, S., Schröder-Preikschat, W., Snelting, G., Weichslgartner, A., & Wildermann, S. (2016). Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution using Invasive Computing. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) (pp. 313-320). Lyon, FR.
Roloff, S., Schafhauser, D., Hannig, F., & Teich, J. (2015). Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. In Proceedings of the 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) (pp. 44:1-44:6). San Francisco, CA, US: Institute of Electrical and Electronics Engineers Inc..
Hannig, F., Lari, V., Boppu, S., Tanase, A.-P., & Reiche, O. (2014). Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Transactions on Embedded Computing Systems, 13(4s), 133:1-133:29. https://dx.doi.org/10.1145/2584660
Teich, J., Henkel, J., Herkersdorf, A., Schmitt-Landsiedel, D., Schröder-Preikschat, W., & Snelting, G. (2011). Invasive Computing: An Overview. In M. Hübner and J. Becker (Eds.), Multiprocessor System-on-Chip - Hardware Design and Tool Integration (pp. 241-268). New York: Springer.
Teich, J. (2008). Invasive Algorithms and Architectures. it - Information Technology, 50(5), 300-310.

Last updated on 2018-30-01 at 04:19