Approximate Computing on FPGAs

Internally funded project


Project Details

Project leader:
Prof. Dr.-Ing. Jürgen Teich

Project members:
Dr.-Ing. Stefan Wildermann
Jorge Alfonso Echavarria Gutiérrez

Contributing FAU Organisations:
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Acronym: AConFPGA
Start date: 13/03/2017


Abstract (technical / expert description):


The goal of our research is a) to investigate novel approximate arithmetic algorithms and their optimization towards FPGA implementation, b) to study new error metrics and a calculus for error propagation of networks of approximate arithmetic modules and c) to investigate novel optimization techniques for design space exploration and synthesis of optimal approximate multi-output Boolean functions for FPGAs.



 


Publications

Echavarria Gutiérrez, J.A., Wildermann, S., & Teich, J. (2018). AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs. In Proceedings of 2018 International Conference on Field Programmable Technology. Naha, Okinawa, JP.
Echavarria Gutiérrez, J.A., Schütz, K., Becher, A., Wildermann, S., & Teich, J. (2018). Can Approximate Computing Reduce Power Consumption on FPGAs? In Proceedings of IEEE International Conference on Electronics Circuits and Systems. Bordeaux, FR.
Echavarria Gutiérrez, J.A., Wildermann, S., & Teich, J. (2018). Design Space Exploration of Multi-output Logic Function Approximations. In Proceedings of the International Conference On Computer Aided Design (ICCAD 2018) (pp. 52:1 - 52:8). San Diego, CA, US.
Echavarria Gutiérrez, J.A., Schütz, K., Becher, A., Wildermann, S., & Teich, J. (2018). Evaluation of Approximate Computing Techniques for Power Reduction on FPGAs. Swissôtel Bremen, DE.
Echavarria Gutiérrez, J.A., Wildermann, S., Potwigin, E., & Teich, J. (2017). Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders. IEEE Embedded Systems Letters, Approximate Computing. https://dx.doi.org/10.1109/LES.2017.2760922
Becher, A., Echavarria Gutiérrez, J.A., Ziener, D., Wildermann, S., & Teich, J. (2016). A LUT-Based Approximate Adder. Washington DC, US: IEEE.
Echavarria Gutiérrez, J.A., Wildermann, S., Becher, A., Teich, J., & Ziener, D. (2016). FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs. In Proceedings of 2016 International Conference on Field Programmable Technology (pp. 213-216). Xi'an, CN.

Last updated on 2018-16-08 at 11:27