SysteMoC: Representing models of computation in SystemC

Internally funded project


Project Details

Project leader:
Joachim Falk

Project members:
Tobias Schwarzer

Contributing FAU Organisations:
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Acronym: SysteMoC
Start date: 01/04/2005


Abstract (technical / expert description):


The automatic identification of models of computation is the key for analysis as weel as efficient synthesis for hardware/sofwtare systems. Programming language like Java, C++, etc. are Turing-complete and mostly restrict the analysis and synthesis. Here, the project SysteMoC is located. Based on the system design language SystemC, coding styles are defined which permit the identification of the underlying model of computation and, hence, allow for analysis and efficient synthesis of hardware/software systems.


Publications
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Xu, Y., Rosales, R., Wang, B., Streubühr, M., Hasholzner, R., Haubelt, C., & Teich, J. (2012). A very fast and quasi-accurate power-state-based system-level power modeling methodology. In Proceedings of the International Conference on Architecture of Computing Systems (ARCS) (pp. 37-49). Munich.
Graf, S., Russ, T., Glaß, M., & Teich, J. (2012). Considering MOST150 during Virtual Prototyping of Automotive E/E Architectures. In Proc. of Automotive meets Electronics (AmE), GMM Fachbericht 72 (pp. 116-121). Dortmund, DE: Berlin, Germany: VDE Verlag.
Zebelein, C., Falk, J., Haubelt, C., & Teich, J. (2012). Exploiting Model-Knowledge in High-Level Synthesis. In Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV’12) (pp. 181-191). Kaiserslautern, DE.
Zhang, L., Streubühr, M., Glaß, M., Teich, J., von Schwerin, A., & Liu, K. (2012). System-Level Modeling and Simulation of Networked PROFINET IO Controllers. In Proc. of the Embedded World Conference. Nuremberg, DE: Kissingen, Germany: WEKA Fachzeitschriften Verlag.
Graf, S., Glaß, M., & Teich, J. (2012). Unreliable Data Transmissions and Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes. In Tagungsunterlagen Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) (pp. 13-24). Kaiserslautern, DE: Hamburg, Germany: Verlag Dr. Kovac.
Kutzer, P., Streubühr, M., Haubelt, C., Teich, J., & von Schwerin, A. (2011). Actor-oriented Modeling of Industrial Ethernet in the Automation Domain Using SystemC. In Proceedings of the Embedded World Conference (pp. 1-10). Nuermberg, DE.
Graf, S., Streubühr, M., Glaß, M., & Teich, J. (2011). Analyzing Automotive Networks using Virtual Prototypes. In Proceedings of the Automotive meets Electronics (AmE2011), GMM Fachbericht 69 (pp. 10-15). Dortmund, Germany, DE: Berlin: VDE VERLAG.
Falk, J., Zebelein, C., Haubelt, C., & Teich, J. (2011). A rule-based static dataflow clustering algorithm for efficient embedded software synthesis. In Proceedings of Design, Automation and Test in Europe (DATE'11) (pp. 521-526). Grenoble, FR.
Glock, S., Fischer, G., Weigel, R., Hasholzner, R., & Ußmüller, T. (2011). A state-based power estimation methodology at system level for integrated RF front-ends. In Semiconductor Conference Dresden 2011 (pp. 1-4). Dresden, Germany: IEEE.
Streubühr, M., Rosales, R., Hasholzner, R., Haubelt, C., & Teich, J. (2011). ESL Power and Performance Estimation for Heterogeneous MPSoCs Using SystemC. In Forum on specification and Design Languages 2011 (pp. 202-209). Oldenbúrg, DE.

Last updated on 2019-10-07 at 14:01