Integration and Coupling of Tightly Coupled Processor Arrays (T01)

Third Party Funds Group - Sub project

Overall project details

Overall project: DFG SFB/Transregio 89 "Invasive Computing"

Project Details

Project leader:
PD Dr.-Ing. Frank Hannig
Prof. Dr.-Ing. Jürgen Teich

Project members:
Dr.-Ing. Alexandru-Petru Tanase

Contributing FAU Organisations:
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen

Funding source: DFG / Sonderforschungsbereich / Transregio (SFB / TRR) (Deutsche Forschungsgemeinschaft (DFG))
Acronym: TCPA_INT
Start date: 01/03/2017
End date: 29/02/2020

Abstract (technical / expert description):

Objective of this transfer project is the analysis of massively parallel accelerator architectures, in particular tightly coupled processor arrays (TCPAs), and their integration into a commercial state-of-the-art embedded microcontroller architecture such as Infineon’s AURIX, or ARM’s Cortex-A series of processors. Concrete research questions, which are of mutual interest for both project partners, include the investigation of suitable ways of coupling while respecting the different performance and bandwidth capabilities of the individual subsystems. Particularly, novel cache-based coupling architectures shall be investigated. The integrated system shall be prototyped and evaluated for selected benchmarks from the domain of advanced driver assistance systems with respect to energy efficiency, area cost, and the predictability of timing as well as safety and reliability.

External Partners

Infineon Technologies AG


Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2017). A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays. In Proceedings of the International Conference on ReConFigurable Computing and FPGA's (ReConFig). Cancun, Mexico, MX.
Sousa, É., Chakraborty, A., Tanase, A.-P., Hannig, F., & Teich, J. (2017). TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays. Poster presentation at Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, MX.

Last updated on 2018-06-09 at 17:01