Energy-efficient Query Processing by Adaptive Dynamic Reconfiguration of FPGA-based, Heterogeneous Accelerator Systems

Eigenmittelfinanziertes Projekt


Details zum Projekt

Projektleiter/in:
Dr.-Ing. Stefan Wildermann

Projektbeteiligte:
Andreas Becher
Dr.-Ing. Daniel Ziener

Beteiligte FAU-Organisationseinheiten:
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Projektstart: 01.10.2014
Projektende: 31.12.2016


Abstract (fachliche Beschreibung):


While CPUs and FPGAs have different strength in terms of power consumption and processing speed, in this project, we want to provide tightly coupled, easy to use accelerator systems which benefit both from the strength of FPGAs and CPUs. To achieve this goal, we study the bottlenecks of each architecture and develop and apply techniques for adaptive optimization of the resulting accelerator systems using partial reconfiguration.


Zuletzt aktualisiert 2018-16-08 um 11:13