GRK 1773: Heterogeneous Image Systems, Project B3

Third Party Funds Group - Sub project

Overall project details

Overall project: RTG 1773: Heterogeneous Image Systems


Project Details

Project leader:
PD Dr.-Ing. Frank Hannig
Prof. Dr.-Ing. Jürgen Teich

Project members:
Oliver Reiche
Mehmet Akif Özkan

Contributing FAU Organisations:
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Funding source: DFG / Graduiertenkolleg (GRK) (Deutsche Forschungsgemeinschaft (DFG))
Acronym: GRK 1773
Start date: 01/10/2012
End date: 31/03/2017
Extension Date: 15/09/2018


Abstract (technical / expert description):


In Teilprojekt B3 werden einheitliche Methoden zur Abbildung von Algorithmen auf heterogene Architekturen untersucht werden. Hierbei sollen im Wesentlichen neue Parallelisierungsmethoden, Partitionierungsverfahren und Code-Generierungstechniken (sowohl Software als auch Hardware-Konfigurationen) speziell für Bildsysteme erforscht werden.


Publications
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Häublein, K., Reichenbach, M., Reiche, O., Özkan, M.A., Fey, D., Hannig, F., & Teich, J. (2016). Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures. In Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (pp. 211-218). Island of Samos, GR.
Fickenscher, J., Reiche, O., Schlumberger, J., Hannig, F., & Teich, J. (2016). Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs. In Proceedings of the 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) (pp. 70-77). Santa Cruz, CA, US.
Reiche, O., Häublein, K., Reichenbach, M., Hannig, F., Teich, J., & Fey, D. (2015). Automatic Optimization of Hardware Accelerators for Image Processing. In Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) (pp. 10-15). Grenoble, FR.
Schmid, M., Reiche, O., Hannig, F., & Teich, J. (2015). Loop Coarsening in C-based High-Level Synthesis. In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 166-173). Toronto, CA: IEEE.
Reiche, O., Häublein, K., Reichenbach, M., Schmid, M., Hannig, F., Teich, J., & Fey, D. (2015). Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge. Journal of Systems Architecture, 61(10), 646-658. https://dx.doi.org/10.1016/j.sysarc.2015.09.004
Membarth, R., Reiche, O., Hannig, F., & Teich, J. (2014). Code Generation for Embedded Heterogeneous Architectures on Android. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE) (pp. 86:1-86:6). Dresden, DE: IEEE.
Schmid, M., Reiche, O., Schmitt, C., Hannig, F., & Teich, J. (2014). Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs. In Proc. of the First International Workshop on FPGAs for Software Programmers (FSP) (pp. 21-26). Munich, DE.
Reiche, O., Schmid, M., Hannig, F., Membarth, R., & Teich, J. (2014). Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (pp. 219-228). New Dehli, IN: New York, NY, USA: ACM.
Membarth, R., Reiche, O., Schmitt, C., Hannig, F., Teich, J., Stürmer, M., & Köstler, H. (2014). Towards a Performance-portable Description of Geometric Multigrid Algorithms using a Domain-specific Language. Journal of Parallel and Distributed Computing, 74(12), 3191-3201. https://dx.doi.org/10.1016/j.jpdc.2014.08.008

Last updated on 2018-05-09 at 11:45