GRK 1773: Heterogeneous Image Systems, Project B3

Third Party Funds Group - Sub project

Overall project details

Overall project: RTG 1773: Heterogeneous Image Systems


Project Details

Project leader:
PD Dr.-Ing. Frank Hannig
Prof. Dr.-Ing. Jürgen Teich

Project members:
Oliver Reiche
Mehmet Akif Özkan

Contributing FAU Organisations:
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Funding source: DFG / Graduiertenkolleg (GRK) (Deutsche Forschungsgemeinschaft (DFG))
Acronym: GRK 1773
Start date: 01/10/2012
End date: 31/03/2017
Extension Date: 15/09/2018


Abstract (technical / expert description):


In Teilprojekt B3 werden einheitliche Methoden zur Abbildung von Algorithmen auf heterogene Architekturen untersucht werden. Hierbei sollen im Wesentlichen neue Parallelisierungsmethoden, Partitionierungsverfahren und Code-Generierungstechniken (sowohl Software als auch Hardware-Konfigurationen) speziell für Bildsysteme erforscht werden.


Publications
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Qiao, B., Reiche, O., Hannig, F., & Teich, J. (2018). Automatic Kernel Fusion for Image Processing DSLs. In Proceedings of the 21th International Workshop on Software and Compilers for Embedded Systems (pp. 76-85). Sankt Goar, DE.
Reiche, O., Özkan, M.A., Hannig, F., Teich, J., & Schmid, M. (2018). Loop Parallelization Techniques for FPGA Accelerator Synthesis. Journal of Signal Processing Systems, 90(1), 3-27. https://dx.doi.org/10.1007/s11265-017-1229-7
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2017). A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis. In Proceedings of the Fourth International Workshop on FPGAs for Software Programmers (FSP). Ghent, BE: VDE.
Reiche, O., Kobylko, C., Hannig, F., & Teich, J. (2017). Auto-vectorization for Image Processing DSLs. In ACM (Eds.), Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) (pp. 21 - 30). Barcelona, ES.
Reiche, O., Özkan, M.A., Membarth, R., Teich, J., & Hannig, F. (2017). Generating FPGA-based Image Processing Accelerators with Hipacc. In IEEE (Eds.), Proceedings of the International Conference On Computer Aided Design (pp. 1026-1033). Irvine, US: IEEE.
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2017). Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing. In 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 155-163). Seattle, US.
Selgrad, K., Lier, A., Dörntlein, J., Reiche, O., & Stamminger, M. (2016). A High-Performance Image Processing DSL for Heterogeneous Architectures. In Proceedings of ELS 9th European Lisp Symposium (pp. 39-46). Krakau, PL: European Lisp Scientific Activities Association.
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2016). FPGA-Based Accelerator Design from a Domain-Specific Language. In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL). Lausanne, CH.
Membarth, R., Reiche, O., Hannig, F., Teich, J., Körner, M., & Eckert, W. (2016). HIPAcc: A Domain-Specific Language and Compiler for Image Processing. IEEE Transactions on Parallel and Distributed Systems, 27(1), 210 - 224. https://dx.doi.org/10.1109/TPDS.2015.2394802
Schmid, M., Reiche, O., Hannig, F., & Teich, J. (2016). HIPAcc. In Dirk Koch, Frank Hannig, and Daniel Ziener (Eds.), FPGAs for Software Programmers. Springer.

Last updated on 2018-05-09 at 11:45