Security by Reconfiguration – Measures against Reverse Engineering and Fault Injection Attacks

Third Party Funds Group - Sub project

Overall project details

Overall project: Security by Reconfiguration

Project Details

Project leader:
Dr.-Ing. Daniel Ziener

Project members:
Jutta Pirkl

Contributing FAU Organisations:
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Funding source: BMBF / Verbundprojekt
Acronym: SecRec
Start date: 01/01/2017
End date: 31/12/2019

Abstract (technical / expert description):

Field Programmable Gate Arrays (FPGAs) represent an efficient platform for cryptographic hardware implementations. However, in order to be hardened against any physical attacks, each security-critical circuit implemented on an FPGA must be protected against (a) side channel analysis, (b) fault injection attacks, and (c) reverse engineering. Accordingly, this project aims to develop techniques that are able to utilize the dynamic reconfiguration capabilities of FPGAs for effective protection mechanisms against the above mentioned class of attacks. The overall project will solve the fundamental problem of cryptographic hardware implementations, namely that these implementations exist only as static circuits and can therefore easily be analyzed.

In particularly, this subproject focuses on the research and development of countermeasures against fault injection attacks and reverse engineering under laboratory conditions.

In SecRec, three renowned research institutes and universities, one medium-size company with excellent credentials and one worldwide leading technology corporation are working together in order to jointly develop innovative approaches for hardware security implementations. These approaches utilizing dynamic reconfiguration in order to protected security implementations against a variety of physical attack classes. In particularly, this subproject focuses on two classes of reconfiguration techniques in order to prevent fault inject attacks and reverse engineering. Local reconfiguration replaces configuration of special FPGA elements, whereas partial dynamic reconfiguration enables a replacement of complete sub circuits at run time. The development of such resistant circuits includes a threat analysis, research and development of countermeasures, as well as the evaluation and demonstration of the gained protection.

Last updated on 2019-09-07 at 14:21