Mehmet Akif Özkan


Graduiertenkolleg 1773 Heterogene Bildsysteme
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Project member

(Heterogeneous Image Systems):
GRK 1773: GRK 1773: Heterogeneous Image Systems, Project B3
PD Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01/10/2012 - 15/09/2018)

HIPAcc: A Domain-Specific Language and GPU Target Code Generator for Image Processing Applications
PD Dr.-Ing. Frank Hannig

Publications (Download BibTeX)

Özkan, M.A., Reiche, O., Qiao, B., Membarth, R., Teich, J., & Hannig, F. (2019). Synthesizing High-Performance Image Processing Applications with Hipacc. In Proceedings of the Demo at the University Booth at Design, Automation and Test in Europe (DATE). Florence, IT.
Özkan, M.A., Pérard-Gayot, A., Membarth, R., Slusallek, P., Teich, J., & Hannig, F. (2018). A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement. In Proceedings of the Fifth International Workshop on FPGAs for Software Programmers. Dublin, IE: VDE.
Reiche, O., Özkan, M.A., Hannig, F., Teich, J., & Schmid, M. (2018). Loop Parallelization Techniques for FPGA Accelerator Synthesis. Journal of Signal Processing Systems, 90(1), 3-27.
Aydin, F., Ugurdag, H.F., Leyent, V.E., Guzel, A.E., Annafianto, N.F.R., Özkan, M.A.,... Erbas, C. (2018). Rapid Design of Real-Time Image Fusion on FPGA Using HLS and Other Techniques. In 2018 IEEE/ACS 15TH INTERNATIONAL CONFERENCE ON COMPUTER SYSTEMS AND APPLICATIONS (AICCSA) (pp. None-None). Aqaba, JO: NEW YORK: IEEE.
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2017). A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis. In Proceedings of the Fourth International Workshop on FPGAs for Software Programmers (FSP). Ghent, BE: VDE.
Reiche, O., Özkan, M.A., Membarth, R., Teich, J., & Hannig, F. (2017). Generating FPGA-based Image Processing Accelerators with Hipacc. In IEEE (Eds.), Proceedings of the International Conference On Computer Aided Design (pp. 1026-1033). Irvine, US: IEEE.
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2017). Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing. In 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 155-163). Seattle, US.
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2016). FPGA-Based Accelerator Design from a Domain-Specific Language. In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL). Lausanne, CH.
Häublein, K., Reichenbach, M., Reiche, O., Özkan, M.A., Fey, D., Hannig, F., & Teich, J. (2016). Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures. In Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (pp. 211-218). Island of Samos, GR.

Last updated on 2018-19-01 at 14:30

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