Mehmet Akif Özkan



Organisation


Graduiertenkolleg 1773 Heterogene Bildsysteme
Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Project member


HIPAcc: A Domain-Specific Language and GPU Target Code Generator for Image Processing Applications
Dr.-Ing. Frank Hannig
(01/01/2009)


Publications (Download BibTeX)


Reiche, O., Özkan, M.A., Hannig, F., Teich, J., & Schmid, M. (2018). Loop Parallelization Techniques for FPGA Accelerator Synthesis. Journal of Signal Processing Systems, 90(1), 3-27. https://dx.doi.org/10.1007/s11265-017-1229-7
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2017). A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis. In Proceedings of the Fourth International Workshop on FPGAs for Software Programmers (FSP). Ghent, BE: VDE.
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2017). Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing. In 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 155-163). Seattle, US.
Reiche, O., Özkan, M.A., Membarth, R., Teich, J., & Hannig, F. (2017). Generating FPGA-based Image Processing Accelerators with Hipacc. In IEEE (Eds.), Proceedings of the International Conference On Computer Aided Design (pp. 1026-1033). Irvine, US: IEEE.
Häublein, K., Reichenbach, M., Reiche, O., Özkan, M.A., Fey, D., Hannig, F., & Teich, J. (2016). Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures. In Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (pp. 211-218). Island of Samos, GR.
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2016). FPGA-Based Accelerator Design from a Domain-Specific Language. In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL). Lausanne, CH.

Last updated on 2018-19-01 at 14:30