PD Dr.-Ing. Frank Hannig

Thomson Researcher ID: G-5213-2014
Scopus Autoren ID: 6602533567



Organisationseinheit


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Preise / Auszeichnungen


2015 : HiPEAC Paper Award: Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures
2013 : Best Paper Award: Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays
2012 : HiPEAC Paper Award: Power Management Strategies for Serial RapidIO Endpoints in FPGAs
2005 : Distinguished Paper: Defragmenting the Module Layout of a Partially Reconfigurable Device



Projektleitung

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HighPerMeshes: Domänenspezifische Programmierung und zielplattformbewusste Compiler-Infrastruktur für Algorithmen auf unstrukturierten Gittern
PD Dr.-Ing. Frank Hannig
(01.04.2017 - 31.03.2020)

(TRR 89: Invasives Rechnen):
TCPA_INT: Integration und Verbindung von eng gekoppelten Prozessorfeldern (T01)
PD Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01.03.2017 - 29.02.2020)

INI.FAU: Parallelisierung und Ressourcenabschätzung von Algorithmen für heterogene FAS-Architekturen
PD Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01.05.2015 - 31.10.2018)

(TRR 89: Invasives Rechnen):
TRR 89: Simulative Entwurfsraumexploration (C02)
PD Dr.-Ing. Frank Hannig
(01.07.2014 - 30.06.2018)

(SPP 1648: Software for Exascale Computing):
ExaStencils: ExaStencils - Advanced Stencil-Code Engineering
PD Dr.-Ing. Frank Hannig; Prof. Dr. Harald Köstler; Prof. Dr. Ulrich Rüde; Prof. Dr.-Ing. Jürgen Teich
(01.01.2013 - 31.12.2018)


Mitarbeit in Forschungsprojekten


(SPP 1648: Software for Exascale Computing):
ExaStencils: ExaStencils - Advanced Stencil-Code Engineering
PD Dr.-Ing. Frank Hannig; Prof. Dr. Harald Köstler; Prof. Dr. Ulrich Rüde; Prof. Dr.-Ing. Jürgen Teich
(01.01.2013 - 31.12.2018)

GRK 1773: Heterogene Bildsysteme
Prof. Dr. Marc Stamminger
(01.10.2012 - 31.03.2017)

(TRR 89: Invasives Rechnen):
TRR 89: Übersetzung und Code-Erzeugung für Invasive Programme (C03)
Prof. Dr.-Ing. Jürgen Teich
(01.07.2010 - 30.06.2018)

TRR 89: DFG SFB/Transregio 89 "Invasives Rechnen"
Prof. Dr.-Ing. Jürgen Teich
(01.07.2010 - 30.06.2022)

Multi-core Architectures and Programming
PD Dr.-Ing. Frank Hannig
(01.01.2009 - 31.12.2014)


Publikationen (Download BibTeX)

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Brand, M., Hannig, F., & Teich, J. (2019). Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic. In Proceedings of the ACM International Conference on Computing Frontiers 2019. Alghero, Sardinia, IT.
Fickenscher, J., Hannig, F., & Teich, J. (2019). DSL-based Acceleration of Automotive Environment Perception and Mapping Algorithms for embedded CPUs, GPUs, and FPGAs. In Proceedings of the ARCS 2019 - 32nd International Conference on Architecture of Computing Systems. Copenhagen, DK.
Membarth, R., Dutta, H., Hannig, F., & Teich, J. (2019). Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. In Transactions on High-Performance Embedded Architectures and Compilers V. (pp. 1-20). Springer.
Qiao, B., Reiche, O., Hannig, F., & Teich, J. (2019). From Loop Fusion to Kernel Fusion: A Domain-specific Approach to Locality Optimization. In Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization (pp. 242-253). Washington DC, USA, US.
Brand, M., Witterauf, M., Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2019). *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing. Concurrency and Computation-Practice & Experience. https://dx.doi.org/10.1002/cpe.5149
Groth, S., Schmitt, C., Teich, J., & Hannig, F. (2019). SYCL Code Generation for Multigrid Methods. In Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems (SCOPES). Sankt Goar, DE: ACM.
Özkan, M.A., Reiche, O., Qiao, B., Membarth, R., Teich, J., & Hannig, F. (2019). Synthesizing High-Performance Image Processing Applications with Hipacc. In Proceedings of the Demo at the University Booth at Design, Automation and Test in Europe (DATE). Florence, IT.
Özkan, M.A., Pérard-Gayot, A., Membarth, R., Slusallek, P., Teich, J., & Hannig, F. (2018). A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement. In Proceedings of the Fifth International Workshop on FPGAs for Software Programmers. Dublin, IE: VDE.
Schmitt, C., Hannig, F., & Teich, J. (2018). A Target Platform Description Language for Parallel Code Generation. In Workshop Proceedings of the 31st GI/ITG International Conference on Architecture of Computing Systems (ARCS) (pp. 59-66). Braunschweig, DE: Berlin: VDE VERLAG GmbH.
Qiao, B., Reiche, O., Hannig, F., & Teich, J. (2018). Automatic Kernel Fusion for Image Processing DSLs. In Proceedings of the 21th International Workshop on Software and Compilers for Embedded Systems (pp. 76-85). Sankt Goar, DE.

Zuletzt aktualisiert 2019-22-01 um 17:50