Dr.-Ing. Frank Hannig

Thomson Researcher ID: G-5213-2014
Scopus Autoren ID: 6602533567



Organisationseinheit


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Preise / Auszeichnungen


2015 : HiPEAC Paper Award: Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures
2013 : Best Paper Award: Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays
2012 : HiPEAC Paper Award: Power Management Strategies for Serial RapidIO Endpoints in FPGAs
2005 : Distinguished Paper: Defragmenting the Module Layout of a Partially Reconfigurable Device



Projektleitung

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HighPerMeshes: Domänenspezifische Programmierung und zielplattformbewusste Compiler-Infrastruktur für Algorithmen auf unstrukturierten Gittern
Dr.-Ing. Frank Hannig
(01.04.2017 - 31.03.2020)

(TRR 89: Invasives Rechnen):
TCPA_INT: Integration und Verbindung von eng gekoppelten Prozessorfeldern (T01)
Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01.03.2017 - 29.02.2020)

INI.FAU: Parallelisierung und Ressourcenabschätzung von Algorithmen für heterogene FAS-Architekturen
Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01.05.2015 - 31.10.2018)

(TRR 89: Invasives Rechnen):
TRR 89: Simulative Entwurfsraumexploration (C02)
Dr.-Ing. Frank Hannig
(01.07.2014 - 30.06.2018)

(SPP 1648: Software for Exascale Computing):
ExaStencils: ExaStencils - Advanced Stencil-Code Engineering
Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01.01.2013 - 31.12.2018)


Mitarbeit in Forschungsprojekten

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(SPP 1648: Software for Exascale Computing):
ExaStencils: ExaStencils - Advanced Stencil-Code Engineering
Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01.01.2013 - 31.12.2018)

(SPP 1648: Software for Exascale Computing):
EXASTENCILS - Advanced Stencil-Code Engineering
Prof. Dr. Ulrich Rüde
(01.11.2012)

GRK 1773: Heterogene Bildsysteme
Prof. Dr. Marc Stamminger
(01.10.2012 - 31.03.2017)

(TRR 89: Invasives Rechnen):
TRR 89: Übersetzung und Code-Erzeugung für Invasive Programme (C03)
Prof. Dr.-Ing. Jürgen Teich
(01.07.2010 - 30.06.2018)

TRR 89: Invasives Rechnen
Prof. Dr.-Ing. Jürgen Teich
(01.07.2010 - 30.06.2022)


Publikationen (Download BibTeX)

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Özkan, M.A., Pérard-Gayot, A., Membarth, R., Slusallek, P., Teich, J., & Hannig, F. (2018). A Journey into DSL Design using Generative Programming: FPGA Mapping of Image Border Handling through Refinement. In Proceedings of the Fifth International Workshop on FPGAs for Software Programmers. Dublin, IE.
Schmitt, C., Hannig, F., & Teich, J. (2018). A Target Platform Description Language for Parallel Code Generation. In Workshop Proceedings of the 31st GI/ITG International Conference on Architecture of Computing Systems (ARCS) (pp. 59-66). Braunschweig, DE: Berlin: VDE VERLAG GmbH.
Qiao, B., Reiche, O., Hannig, F., & Teich, J. (2018). Automatic Kernel Fusion for Image Processing DSLs. In Proceedings of the 21th International Workshop on Software and Compilers for Embedded Systems (pp. 76-85). Sankt Goar, DE.
Schmitt, C., Kronawitter, S., Hannig, F., Teich, J., & Lengauer, C. (2018). Automating the Development of High-Performance Multigrid Solvers. Proceedings of the IEEE. https://dx.doi.org/10.1109/JPROC.2018.2854229
Fickenscher, J., Hannig, F., Teich, J., & Bouzouraa, M.E. (2018). Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. (pp. 298-306). Funchal, Madeira, Portugal, PT: SCITEPRESS.
Fickenscher, J., Schlumberger, J., Hannig, F., Bouzouraa, M.E., & Teich, J. (2018). Cell-based Update Algorithm for Occupancy Grid Maps and new Hybrid Map for ADAS on Embedded GPUs. In IEEE (Eds.), (pp. 443-448). Dresden, Germany, DE: IEEE.
Fickenscher, J., Hannig, F., Bouzouraa, M.E., & Teich, J. (2018). Embedded GPUs in Future Automated Cars. Dresden, DE.
Sousa, É., Witterauf, M., Brand, M., Tanase, A.-P., Hannig, F., & Teich, J. (2018). Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. Milan, Italy.
Reiche, O., Özkan, M.A., Hannig, F., Teich, J., & Schmid, M. (2018). Loop Parallelization Techniques for FPGA Accelerator Synthesis. Journal of Signal Processing Systems, 90(1), 3-27. https://dx.doi.org/10.1007/s11265-017-1229-7
Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A.,... Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In Proceedings of the 26th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM). Boulder, CO, USA, US: ACM.

Zuletzt aktualisiert 2018-16-08 um 17:12