Moritz Schmid



Organisation


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Awards / Honours


2012 : HiPEAC Paper Award: Power Management Strategies for Serial RapidIO Endpoints in FPGAs


Project member


MMSys: Motion Management System
PD Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01/11/2009 - 30/04/2013)

Serielle Hochgeschwindigkeitsverbindungen für medizinische Bildverarbeitung
PD Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(15/04/2008 - 30/04/2012)


Publications (Download BibTeX)

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Reiche, O., Özkan, M.A., Hannig, F., Teich, J., & Schmid, M. (2018). Loop Parallelization Techniques for FPGA Accelerator Synthesis. Journal of Signal Processing Systems, 90(1), 3-27. https://dx.doi.org/10.1007/s11265-017-1229-7
Schmitt, C., Schmid, M., Kuckuk, S., Köstler, H., Teich, J., & Hannig, F. (2018). Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. Parallel Processing Letters, 28(4). https://dx.doi.org/10.1142/S0129626418500160
Bhadouria, V.S., Tanase, A.-P., Schmid, M., Hannig, F., Teich, J., & Ghoshal, D. (2016). A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. Journal of Signal Processing Systems, 89(2), 225-242. https://dx.doi.org/10.1007/s11265-016-1187-5
Schmid, M., Schmitt, C., Hannig, F., Malazgirt, G.A., Sönmez, N., Yurdakul, A., & Cristal, A. (2016). Big Data and HPC Acceleration with Vivado HLS. In Dirk Koch, Frank Hannig, and Daniel Ziener (Eds.), FPGAs for Software Programmers (pp. 115-136). Springer.
Schmid, M., Reiche, O., Hannig, F., & Teich, J. (2016). HIPAcc. In Dirk Koch, Frank Hannig, and Daniel Ziener (Eds.), FPGAs for Software Programmers Springer.
Schmitt, C., Schmid, M., Hannig, F., Teich, J., Kuckuk, S., & Köstler, H. (2015). Generation of Multigrid-based Numerical Solvers for FPGA Accelerators. In Proceedings of the 2nd International Workshop on High-Performance Stencil Computations (HiStencils) (pp. 9-15). Amsterdam, NL.
Schmid, M., Reiche, O., Hannig, F., & Teich, J. (2015). Loop Coarsening in C-based High-Level Synthesis. In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 166-173). Toronto, CA: IEEE.
Schmid, M. (2015). Rapid Prototyping for Hardware Accelerators in the Medical Imaging Domain (Dissertation).
Reiche, O., Häublein, K., Reichenbach, M., Schmid, M., Hannig, F., Teich, J., & Fey, D. (2015). Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge. Journal of Systems Architecture, 61(10), 646-658. https://dx.doi.org/10.1016/j.sysarc.2015.09.004
Schmid, M., Apelt, N., Hannig, F., & Teich, J. (2014). An Image Processing Library for C-based High-Level Synthesis. In Proc. of Field-Programmable Logic and Applications (FPL). Munich, DE: New York, NY, USA: IEEE Press.

Last updated on 2016-27-05 at 02:01