Deepak Gangadharan, Ph.D.



Organisation


Sonderforschungsbereich/Transregio 89 Invasives Rechnen


Publications (Download BibTeX)


Weichslgartner, A., Wildermann, S., Gangadharan, D., Glaß, M., & Teich, J. (2018). A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. ACM Transactions on Embedded Computing Systems.
Gangadharan, D., Sousa, É., Lari, V., Hannig, F., & Teich, J. (2015). Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. In Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR) (pp. 398-403). Pacific Grove, CA, US: IEEE Computer Society.
Weichslgartner, A., Gangadharan, D., Wildermann, S., Glaß, M., & Teich, J. (2014). DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014) (pp. 10). New Delhi, IN: Association for Computing Machinery, Inc.
Gangadharan, D., Teich, J., & Chakraborty, S. (2014). Quality-aware video decoding on thermally-constrained MPSoC platforms. In Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 256-263). Zurich, CH: Institute of Electrical and Electronics Engineers Inc..
Sousa, É., Gangadharan, D., Hannig, F., & Teich, J. (2014). Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures. In Proceedings of the EUROMICRO Digital System Design Conference (DSD) (pp. 74-81). Verona, IT: Institute of Electrical and Electronics Engineers Inc..
Gangadharan, D., Tanase, A.-P., Hannig, F., & Teich, J. (2014). Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays. In Proceedings of the DATE Friday Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES). Dresden, Germany.

Last updated on 2018-26-10 at 14:15