Mehrdad Biglari



Organisationseinheit


Lehrstuhl für Informatik 3 (Rechnerarchitektur)


Publikationen (Download BibTeX)


Biglari, M., Lieske, T., & Fey, D. (2019). Reducing Hibernation Energy and Degradation in Bipolar ReRAM-Based Non-Volatile Processors. IEEE Transactions on Nanotechnology, to appear. https://dx.doi.org/10.1109/TNANO.2019.2922363
Biglari, M., Lieske, T., & Fey, D. (2018). High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States. In Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures (pp. 19 - 24). Athens, Greece: New York, NY, USA: ACM.
Lieske, T., Biglari, M., & Fey, D. (2018). Multi-Level Memristive Voltage Divider: Programming Scheme Trade-offs. In Proceedings of the International Symposium on Memory Systems (pp. 259-268). Alexandria, Virginia, US: New York, NY, USA: ACM.
Biglari, M., & Fey, D. (2017, March). A Non-Volatile Flip-Flop Using Memristive Voltage Divider. Poster presentation at IEEE/ACM Design Automation and Test in Europe (DATE), Workshop on Emerging Memory Solutions - Technology, Manufacturing, Architectures, Design and Test, Lausanne, CH.
Biglari, M., & Fey, D. (2017). Memristive Voltage Divider: A Bipolar ReRAM-based Unit for Non-Volatile Flip-Flops. In MEMSYS'17 Proceedings of the International Symposium on Memory Systems (pp. 217-222). Alexandria, VA, US: ACM.
Wust, D., Biglari, M., Knödtel, J., Reichenbach, M., Söll, C., & Fey, D. (2017). Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment. In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017 27th International Symposium on (pp. 1-7). Thessaloniki, GR: IEEE.
Biglari, M., Barijough, K.M., Goudarzi, M., & Pourmohseni, B. (2016). A Fine-Grained Configurable Cache Architecture for Soft Processors. In 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS) (pp. 1-6). Tehran, IR: IEEE.
Fey, D., Reichenbach, M., Söll, C., Biglari, M., Röber, J., & Weigel, R. (2016). Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits. In Proceedings of the Second International Symposium on Memory Systems (pp. 442-454). Alexandria, VA, US: ACM.
Biglari, M., Qasemi, E., & Pourmohseni, B. (2014). Maestro: A High Performance AES Encryption/Decryption System. In The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013) (pp. 145-148). Tehran, IR: IEEE.

Zuletzt aktualisiert 2017-18-03 um 03:44