Dr.-Ing. Alexandru-Petru Tanase



Organisationseinheit


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen


Preise / Auszeichnungen


2013 : Best Paper Award: Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays


Mitarbeit in Forschungsprojekten


(TRR 89: Invasives Rechnen):
TCPA_INT: Integration und Verbindung von eng gekoppelten Prozessorfeldern (T01)
PD Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01.03.2017 - 29.02.2020)

(TRR 89: Invasives Rechnen):
TRR 89: Übersetzung und Code-Erzeugung für Invasive Programme (C03)
Prof. Dr.-Ing. Jürgen Teich
(01.07.2010 - 30.06.2018)

TRR 89: DFG SFB/Transregio 89 "Invasives Rechnen"
Prof. Dr.-Ing. Jürgen Teich
(01.07.2010 - 30.06.2022)

PARO: Dedizierte massiv parallele Systeme
PD Dr.-Ing. Frank Hannig
(03.01.2000)


Publikationen (Download BibTeX)

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Tanase, A.-P., Witterauf, M., Sousa, É., Lari, V., Hannig, F., & Teich, J. (2016). LoopInvader: A Compiler for Tightly Coupled Processor Arrays. In Tool presentation at the University Booth. Dresden, DE.
Witterauf, M., Tanase, A.-P., Hannig, F., & Teich, J. (2016). Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays. In Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). London, GB.
Lari, V., Weichslgartner, A., Tanase, A.-P., Witterauf, M., Khosravi, F., Teich, J.,... Becker, J. (2016). Providing Fault Tolerance Through Invasive Computing. it - Information Technology, 58(6), 309-238.
Lari, V., Tanase, A.-P., Teich, J., Witterauf, M., Khosravi, F., Hannig, F., & Meyer, B. (2015). A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (pp. 1-8). Montreal, CA: Institute of Electrical and Electronics Engineers Inc..
Witterauf, M., Tanase, A.-P., Hannig, F., & Teich, J. (2015). Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing. In Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (pp. 205-208). Fiuggi, IT: HiPEAC.
Witterauf, M., Tanase, A.-P., Teich, J., Lari, V., Zwinkau, A., & Snelting, G. (2015). Adaptive fault tolerance through invasive computing. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (pp. 1-8). Montreal, CA: Institute of Electrical and Electronics Engineers Inc..
Tanase, A.-P., Witterauf, M., Teich, J., Hannig, F., & Lari, V. (2015). On-demand fault-tolerant loop processing on massively parallel processor arrays. In In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 194-201). Toronto, CA: Institute of Electrical and Electronics Engineers Inc..
Tanase, A.-P., Witterauf, M., Hannig, F., & Teich, J. (2015). Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. In Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) (pp. 188-197). Austin, US: Institute of Electrical and Electronics Engineers Inc..
Teich, J., Lari, V., Tanase, A.-P., Witterauf, M., Khosravi, F., & Meyer, B. (2015). Techniques for on-demand structural redundancy for massively parallel processor arrays. Journal of Systems Architecture, 61(10), 615-627. https://dx.doi.org/10.1016/j.sysarc.2015.10.004
Schmid, M., Tanase, A.-P., Hannig, F., Teich, J., Bhadouria, V.S., & Ghoshal, D. (2014). Domain-Specific Augmentations for High-Level Synthesis. In Proc. of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 173-177). Zurich, CH: New York, NY, USA: Institute of Electrical and Electronics Engineers.

Zuletzt aktualisiert 2018-24-04 um 16:02

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