Dr.-Ing. Alexandru-Petru Tanase



Organisation


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen


Awards / Honours


2013 : Best Paper Award: Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays


Project member


(TRR 89: Invasive Computing):
TCPA_INT: Integration and Coupling of Tightly Coupled Processor Arrays (T01)
PD Dr.-Ing. Frank Hannig; Prof. Dr.-Ing. Jürgen Teich
(01/03/2017 - 29/02/2020)

(TRR 89: Invasive Computing):
TRR 89: Compilation and Code Generation for Invasive Programs (C03)
Prof. Dr.-Ing. Jürgen Teich
(01/07/2010 - 30/06/2018)

TRR 89: DFG SFB/Transregio 89 "Invasive Computing"
Prof. Dr.-Ing. Jürgen Teich
(01/07/2010 - 30/06/2022)

PARO: Dedizierte massiv parallele Systeme
PD Dr.-Ing. Frank Hannig
(03/01/2000)


Publications (Download BibTeX)

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Brand, M., Witterauf, M., Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2019). *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing. Concurrency and Computation-Practice & Experience. https://dx.doi.org/10.1002/cpe.5149
Sousa, É., Witterauf, M., Brand, M., Tanase, A.-P., Hannig, F., & Teich, J. (2018). Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. In Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). Milan, Italy.
Tanase, A.-P., Hannig, F., & Teich, J. (2018). Symbolic Parallelization of Nested Loop Programs. Springer.
Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2017). A Reconfigurable Memory Architecture for System Integration of Coarse-Grained Reconfigurable Arrays. Cancun, Mexico, MX.
Brand, M., Hannig, F., Tanase, A.-P., & Teich, J. (2017, July). Efficiency in ILP Processing by Using Orthogonality. Poster presentation at The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017), Seattle, US.
Brand, M., Hannig, F., Tanase, A.-P., & Teich, J. (2017). Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. In 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (pp. 5-12). Korea University, Seoul, Korea, KR.
Tanase, A.-P., Witterauf, M., Teich, J., & Hannig, F. (2017). Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Transactions on Embedded Computing Systems, 17(2), 31:1-31:27. https://dx.doi.org/10.1145/3092952
Tanase, A.-P. (2017). Symbolic Parallelization of Nested Loop Programs (Dissertation).
Sousa, É., Chakraborty, A., Tanase, A.-P., Hannig, F., & Teich, J. (2017). TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays. Poster presentation at Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, MX.
Bhadouria, V.S., Tanase, A.-P., Schmid, M., Hannig, F., Teich, J., & Ghoshal, D. (2016). A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. Journal of Signal Processing Systems, 89(2), 225-242. https://dx.doi.org/10.1007/s11265-016-1187-5

Last updated on 2018-24-04 at 16:02