Michael Witterauf



Organisation


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen


Project member


(TRR 89: Invasive Computing):
TRR 89: Simulative Design Space Exploration (C02)
PD Dr.-Ing. Frank Hannig
(01/07/2014 - 30/06/2018)

(TRR 89: Invasive Computing):
TRR 89: Compilation and Code Generation for Invasive Programs (C03)
Prof. Dr.-Ing. Jürgen Teich
(01/07/2010 - 30/06/2018)

TRR 89: DFG SFB/Transregio 89 "Invasive Computing"
Prof. Dr.-Ing. Jürgen Teich
(01/07/2010 - 30/06/2022)

PARO: Dedizierte massiv parallele Systeme
PD Dr.-Ing. Frank Hannig
(03/01/2000)


Publications (Download BibTeX)

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Brand, M., Witterauf, M., Hannig, F., & Teich, J. (2019). Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic. In ACM (Eds.), Proceedings of the ACM International Conference on Computing Frontiers 2019 (pp. 215 - 219). Alghero, Sardinia, IT.
Heidorn, C., Witterauf, M., Hannig, F., & Teich, J. (2019). Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. Journal of Computers, 14(8), 541-556. https://dx.doi.org/10.17706/jcp.14.8.541-556
Witterauf, M., Hannig, F., & Teich, J. (2019). Polyhedral Fragments: An Efficient Representation for Symbolically Generating Code for Processor Arrays. In Proceedings of the International Conference on Formal Methods and Models for System Design (MEMOCODE). San Diego.
Brand, M., Witterauf, M., Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2019). *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing. Concurrency and Computation-Practice & Experience. https://dx.doi.org/10.1002/cpe.5149
Sousa, É., Witterauf, M., Brand, M., Tanase, A.-P., Hannig, F., & Teich, J. (2018). Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. In Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). Milan, Italy.
Witterauf, M., & Teich, J. (2018). Run-time Requirement Enforcement for Loop Programs on Processor Arrays. In ACM, IEEE (Eds.), Proceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) (pp. 1-11). Peking, CN.
Witterauf, M., Hannig, F., & Teich, J. (2017). Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates. In Proceedings of the Symposium on Rapid System Prototyping. Seoul, South Korea, KR.
Tanase, A.-P., Witterauf, M., Teich, J., & Hannig, F. (2017). Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Transactions on Embedded Computing Systems, 17(2), 31:1-31:27. https://dx.doi.org/10.1145/3092952
Tanase, A.-P., Witterauf, M., Sousa, É., Lari, V., Hannig, F., & Teich, J. (2016). LoopInvader: A Compiler for Tightly Coupled Processor Arrays. In Tool presentation at the University Booth. Dresden, DE.
Witterauf, M., Tanase, A.-P., Hannig, F., & Teich, J. (2016). Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays. In Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). London, GB.

Last updated on 2016-27-05 at 05:05