Michael Witterauf



Organisationseinheit


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen


Mitarbeit in Forschungsprojekten


(TRR 89: Invasives Rechnen):
TRR 89: Simulative Entwurfsraumexploration (C02)
PD Dr.-Ing. Frank Hannig
(01.07.2014 - 30.06.2018)

(TRR 89: Invasives Rechnen):
TRR 89: Übersetzung und Code-Erzeugung für Invasive Programme (C03)
Prof. Dr.-Ing. Jürgen Teich
(01.07.2010 - 30.06.2018)

TRR 89: DFG SFB/Transregio 89 "Invasives Rechnen"
Prof. Dr.-Ing. Jürgen Teich
(01.07.2010 - 30.06.2022)

PARO: Dedizierte massiv parallele Systeme
PD Dr.-Ing. Frank Hannig
(03.01.2000)


Publikationen (Download BibTeX)

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Brand, M., Witterauf, M., Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2019). *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing. Concurrency and Computation-Practice & Experience. https://dx.doi.org/10.1002/cpe.5149
Sousa, É., Witterauf, M., Brand, M., Tanase, A.-P., Hannig, F., & Teich, J. (2018). Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. In Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). Milan, Italy.
Witterauf, M., & Teich, J. (2018). Run-time Requirement Enforcement for Loop Programs on Processor Arrays. In ACM, IEEE (Eds.), Proceedings of the 16th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) (pp. 1-11). Peking, CN.
Witterauf, M., Hannig, F., & Teich, J. (2017). Constructing Fast and Cycle-Accurate Simulators for Configurable Accelerators Using C++ Templates. In Proceedings of the Symposium on Rapid System Prototyping. Seoul, South Korea, KR.
Tanase, A.-P., Witterauf, M., Teich, J., & Hannig, F. (2017). Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Transactions on Embedded Computing Systems, 17(2), 31:1-31:27. https://dx.doi.org/10.1145/3092952
Tanase, A.-P., Witterauf, M., Sousa, É., Lari, V., Hannig, F., & Teich, J. (2016). LoopInvader: A Compiler for Tightly Coupled Processor Arrays. In Tool presentation at the University Booth. Dresden, DE.
Witterauf, M., Tanase, A.-P., Hannig, F., & Teich, J. (2016). Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays. In Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). London, GB.
Lari, V., Weichslgartner, A., Tanase, A.-P., Witterauf, M., Khosravi, F., Teich, J.,... Becker, J. (2016). Providing Fault Tolerance Through Invasive Computing. it - Information Technology, 58(6), 309-238.
Lari, V., Tanase, A.-P., Teich, J., Witterauf, M., Khosravi, F., Hannig, F., & Meyer, B. (2015). A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (pp. 1-8). Montreal, CA: Institute of Electrical and Electronics Engineers Inc..
Witterauf, M., Tanase, A.-P., Hannig, F., & Teich, J. (2015). Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing. In Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (pp. 205-208). Fiuggi, IT: HiPEAC.

Zuletzt aktualisiert 2016-27-05 um 05:05