Oliver Reiche



Organisation


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)


Project member


HIPAcc: A Domain-Specific Language and GPU Target Code Generator for Image Processing Applications
Dr.-Ing. Frank Hannig
(01/01/2009)


Publications (Download BibTeX)

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Qiao, B., Reiche, O., Hannig, F., & Teich, J. (2018). Automatic Kernel Fusion for Image Processing DSLs. In Proceedings of the 21th International Workshop on Software and Compilers for Embedded Systems. Sankt Goar, DE.
Reiche, O., Özkan, M.A., Hannig, F., Teich, J., & Schmid, M. (2018). Loop Parallelization Techniques for FPGA Accelerator Synthesis. Journal of Signal Processing Systems, 90(1), 3-27. https://dx.doi.org/10.1007/s11265-017-1229-7
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2017). A Highly Efficient and Comprehensive Image Processing Library for C++-based High-Level Synthesis. In Proceedings of the Fourth International Workshop on FPGAs for Software Programmers (FSP). Ghent, BE: VDE.
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2017). Hardware Design and Analysis of Efficient Loop Coarsening and Border Handling for Image Processing. In 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 155-163). Seattle, US.
Reiche, O., Kobylko, C., Hannig, F., & Teich, J. (2017). Auto-vectorization for Image Processing DSLs. In ACM (Eds.), Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) (pp. 21 - 30). Barcelona, ES.
Reiche, O., Özkan, M.A., Membarth, R., Teich, J., & Hannig, F. (2017). Generating FPGA-based Image Processing Accelerators with Hipacc. In IEEE (Eds.), Proceedings of the International Conference On Computer Aided Design (pp. 1026-1033). Irvine, US: IEEE.
Fickenscher, J., Reiche, O., Schlumberger, J., Hannig, F., & Teich, J. (2016). Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs. In Proceedings of the 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) (pp. 70-77). Santa Cruz, CA, US.
Häublein, K., Reichenbach, M., Reiche, O., Özkan, M.A., Fey, D., Hannig, F., & Teich, J. (2016). Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures. In Proceedings of the 16th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) (pp. 211-218). Island of Samos, GR.
Membarth, R., Reiche, O., Hannig, F., Teich, J., Körner, M., & Eckert, W. (2016). HIPAcc: A Domain-Specific Language and Compiler for Image Processing. IEEE Transactions on Parallel and Distributed Systems, 27(1), 210 - 224. https://dx.doi.org/10.1109/TPDS.2015.2394802
Özkan, M.A., Reiche, O., Hannig, F., & Teich, J. (2016). FPGA-Based Accelerator Design from a Domain-Specific Language. In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL). Lausanne, CH.

Last updated on 2017-09-08 at 14:44