Dr. Jan Eitzinger



Organisationseinheit


Regionales Rechenzentrum Erlangen (RRZE)


Mitarbeit in Forschungsprojekten


ProPE: Prozessorientierte Dienststruktur für Perfomance Engineering von wissenschaftlicher Software an deutschen HPC-Zentren
Prof. Dr. Gerhard Wellein
(01.01.2017 - 31.12.2019)

MeTacca: Metaprogrammierung für Beschleunigerarchitekturen
Prof. Dr. Harald Köstler; Prof. Dr. Gerhard Wellein
(01.01.2017 - 31.12.2019)


Publikationen (Download BibTeX)

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Schmitt, J., Köstler, H., Eitzinger, J., & Membarth, R. (2018). Unified Code Generation for the Parallel Computation of Pairwise Interactions using Partial Evaluation. In IEEE (Eds.), Proceedings of the 17th International Symposium on Parallel and Distributed Computing (ISPDC) (pp. 17-24). Geneva, CH.
Hammer, J., Eitzinger, J., Hager, G., & Wellein, G. (2017). Kerncraft: A Tool for Analytic Performance Modeling of Loop Kernels. In Niethammer C, Gracia J, Hilbrich T, Knüpfer A, Resch MM, Nagel WE (Eds.), Tools for High Performance Computing 2016 (pp. 1--22). Stuttgart, Germany: Cham: Springer International Publishing.
Röhl, T., Eitzinger, J., Hager, G., & Wellein, G. (2017). LIKWID monitoring stack: A flexible framework enabling job specific performance monitoring for the masses. (pp. 781-784). Institute of Electrical and Electronics Engineers Inc..
Hofmann, J., Fey, D., Riedmann, M., Eitzinger, J., Hager, G., & Wellein, G. (2017). Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors. Concurrency and Computation-Practice & Experience, 29(9). https://dx.doi.org/10.1002/cpe.3921
Hofmann, J., Fey, D., Eitzinger, J., Hager, G., & Wellein, G. (2016). Analysis of intel’s haswell microarchitecture using the ECM model and microbenchmarks. Springer Verlag.
Hofmann, J., Fey, D., Eitzinger, J., Hager, G., & Wellein, G. (2016). Analysis of Intel's Haswell Microarchitecture Using the ECM Model and Microbenchmarks. In Architecture of Computing Systems -- ARCS 2016: 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings (pp. 210-222). Nuremberg: Cham: Springer International Publishing.
Hager, G., Eitzinger, J., Habich, J., & Wellein, G. (2016). Exploring performance and power properties of modern multi-core chips via simple machine models. Concurrency and Computation-Practice & Experience, 28(2), 189-210. https://dx.doi.org/10.1002/cpe.3180
Hofmann, J., Fey, D., Riedman, M., Eitzinger, J., Hager, G., & Wellein, G. (2016). Performance analysis of the Kahan-enhanced scalar product on current multi-corecore and many-core processors. Concurrency and Computation-Practice & Experience, 28(12). https://dx.doi.org/10.1002/cpe.3921
Hammer, J., Hager, G., Eitzinger, J., & Wellein, G. (2015). Automatic loop kernel analysis and performance modeling with kerncraft. Association for Computing Machinery, Inc.
Wellein, G., Eitzinger, J., Hager, G., & Röhl, T. (2015). Overhead Analysis of Performance Counter Measurements. (pp. 176-185). Institute of Electrical and Electronics Engineers Inc..

Zuletzt aktualisiert 2018-04-10 um 23:51