Dr.-Ing. Daniel Ziener


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

Awards / Honours

2015 : Best Paper Award: Reliability of Space-Grade vs. COTS SRAM-based FPGA in N-Modular Redundancy
2014 : HiPEAC Paper Award: A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor

Project lead

(Security by Reconfiguration):
SecRec: Security by Reconfiguration – Measures against Reverse Engineering and Fault Injection Attacks
Dr.-Ing. Daniel Ziener
(01/01/2017 - 31/12/2019)

SatFPGA: Reliable FPGA-based Adaptive Systems for Space and Avionics Applications
Prof. Dr.-Ing. Jürgen Teich; Dr.-Ing. Daniel Ziener
(01/04/2013 - 31/12/2014)

DRAQA: Dynamically Reconfigurable SQL Accelerator based on FPGAs
Prof. Dr.-Ing. Jürgen Teich; Dr.-Ing. Daniel Ziener
(01/10/2011 - 30/09/2014)

DCCD: Concepts for Implementing and Optimizing a Prototypical Design of a Modular and Configurable Data Consolidation Device Unit for Civil Air Planes
Prof. Dr.-Ing. Jürgen Teich; Dr.-Ing. Daniel Ziener
(15/09/2010 - 14/09/2014)

Project member

Energy-efficient Query Processing by Adaptive Dynamic Reconfiguration of FPGA-based, Heterogeneous Accelerator Systems
Dr.-Ing. Stefan Wildermann
(01/10/2014 - 31/12/2016)

2D/3D Video: 2D/3D Video Surveillance
Prof. Dr.-Ing. Jürgen Teich
(01/10/2009 - 30/04/2013)

Publications (Download BibTeX)

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Posewsky, T., & Ziener, D. (2018). A Flexible FPGA-based Inference Architecture for Pruned Deep Neural Networks. In Proceedings of the International Conference on Architecture of Computing Systems. Braunschweig, DE.
Ziener, D. (2017). Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems (Habilitation).
Schmidt, B., Ziener, D., Teich, J., & Zöllner, C. (2017). Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning. Integration-The Vlsi Journal.
Becher, A., Echavarria Gutiérrez, J.A., Ziener, D., Wildermann, S., & Teich, J. (2016). A LUT-Based Approximate Adder. Washington DC, US: IEEE.
Posewsky, T., & Ziener, D. (2016). Efficient Deep Neural Network Acceleration through FPGA-based Batch Processing. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). Cancún, MX.
Echavarria Gutiérrez, J.A., Wildermann, S., Becher, A., Teich, J., & Ziener, D. (2016). FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs. In Proceedings of 2016 International Conference on Field Programmable Technology (pp. 213-216). Xi'an, CN.
Ziener, D., Weber, H., Vogt, J.-S., Schürfeld, U., Meyer-Wegener, K., Teich, J.,... Bauer, F. (2016). FPGA-Based Dynamically Reconfigurable SQL Query Processing. ACM Transactions on Reconfigurable Technology and Systems, 9(4), 25:1-25:24. https://dx.doi.org/10.1145/2845087
Koch, D., Hannig, F., & Ziener, D. (Eds.) (2016). FPGAs for Software Programmers. Berlin; Heidelberg: Springer-Verlag.
Koch, D., Hannig, F., & Ziener, D. (Eds.) (2016). FPGAs for Software Programmers. Springer.
Koch, D., Ziener, D., & Hannig, F. (2016). FPGA versus Software Programming - Why, When, and How? In Dirk Koch, Frank Hannig, and Daniel Ziener (Eds.), FPGAs for Software Programmers (pp. 1-21).

Last updated on 2016-05-05 at 05:05