Johannes Knödtel

Lehrstuhl für Informatik 3 (Rechnerarchitektur)

Interfacing real-time and offline power system simulation tools using UDP or FPGA systems (2022) Scheibe C, Kuri A, Feng Y, Zhao L, Xiong X, La Seta P, Liang XP, et al. Journal article RISC-V3: A RISC-V Compatible CPU with a Data Path Based on Redundant Number Systems (2021) Reichenbach M, Knödtel J, Rachuj S, Fey D Journal article Simulating large neural networks embedding MLC RRAM as weight storage considering device variations (2021) Fritscher M, Knödtel J, Reiser D, Mallah M, Pechmann S, Fey D, Reichenbach M Conference contribution, Original article Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks (2021) Fritscher M, Knödtel J, Mallah M, Pechmann S, Quesada EPB, Rizzi T, Wenger C, Reichenbach M Conference contribution, Conference Contribution A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories (2020) Knödtel J, Fritscher M, Reiser D, Fey D, Breiling M, Reichenbach M Conference contribution, Conference Contribution Simulating memristive systems in mixed-signal mode using commercial design tools (2019) Fritscher M, Knödtel J, Reichenbach M, Fey D Conference contribution Optimizing Multi-State Reliability in ReRAM Arrays using an Automated Device Selection Method (2019) Peschel J, Knödtel J, Pérez E, Reichenbach M, Wenger C, Fey D Conference contribution, Abstract of lecture A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs (2018) Knödtel J, Schwabe W, Lieske T, Reichenbach M, Fey D Conference contribution, Conference Contribution A programmable ternary CPU using hybrid CMOS/memristor circuits (2018) Wust D, Fey D, Knödtel J Journal article, Original article Prototyping Memristors in Digital Systems with an FPGA-Based Testing Environment (2017) Wust D, Biglari M, Knödtel J, Reichenbach M, Söll C, Fey D Conference contribution, Original article