Srinivas Boppu


Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen

Project member

(TRR 89: Invasive Computing):
TRR 89: Validation and Demonstrator (Z02)
PD Dr.-Ing. Frank Hannig
(01/07/2010 - 30/06/2022)

TRR 89: DFG SFB/Transregio 89 "Invasive Computing"
Prof. Dr.-Ing. Jürgen Teich
(01/07/2010 - 30/06/2022)

Publications (Download BibTeX)

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Boppu, S. (2015). Code Generation for Tightly Coupled Processor Arrays (Dissertation).
Teich, J., Boppu, S., Hannig, F., & Lari, V. (2015). Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays. In Luk, Wayne, Constantinides, George A. (Eds.), Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung. (pp. 167-206).
Boppu, S., Hannig, F., & Teich, J. (2014). Compact Code Generation for Tightly-Coupled Processor Arrays. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 77(1-2), 5-29.
Hannig, F., Lari, V., Boppu, S., Tanase, A.-P., & Reiche, O. (2014). Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Transactions on Embedded Computing Systems, 13(4s), 133:1-133:29.
Glocker, E., Boppu, S., Chen, Q., Schlichtmann, U., Teich, J., & Schmitt-Landsiedel, D. (2014). Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs). Advances in Radio Science, 12, 103-109.
Boppu, S., Hannig, F., & Teich, J. (2013). Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators. In Proc. 24th International Conference on Application-Specific Systems, Architectures and Processors (pp. 10-17). Washington, DC, US: New York, NY, USA: Institute of Electrical and Electronics Engineers.
Hannig, F., Schmid, M., Lari, V., Boppu, S., & Teich, J. (2013). System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures. In Proc. ACM International Conference on Computing Frontiers (pp. 1-4). Ischia, IT: New York, NY, USA: ACM Press.
Boppu, S., Lari, V., Hannig, F., & Teich, J. (2013). Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures. In Proc. Synopsys Users Group Conference (pp. 1-15). Munich, DE.
Muddasani, S., Boppu, S., Hannig, F., Kuzmin, B., Lari, V., & Teich, J. (2012). A Prototype of an Invasive Tightly-Coupled Processor Array. In Proc. of the 2012 Conference on Design and Architectures for Signal and Image Processing (DASIP) (pp. 393-394). Karlsruhe, DE: New York, NY, USA: IEEE Press.
Lari, V., Muddasani, S., Boppu, S., Hannig, F., & Teich, J. (2012). Design of low power on-chip processor arrays. In Proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) (pp. 165-168). Delft, NL.

Last updated on 2016-04-06 at 02:01