Sonderforschungsbereich/Transregio 89 Invasives Rechnen

Address:
Cauerstraße 11
91058 Erlangen



Subordinate Organisational Units

Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP A01 Grundlagen Invasiven Rechnens
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP A04 Charakterisierung und Analyse Invasiver Algorithmen
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP B02 Invasive eng gekoppelte Prozessorfelder
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C01 Invasives Laufzeitunterstützungssystem (iRTSS)
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C03 Übersetzung und Code-Erzeugung für Invasive Programme
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C05 IT-Sicherheit bei invasivem Rechnen
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP Z02 Valdidierung und Demonstrator
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP Z Zentrale Dienste des SFB/Transregio und Öffentlichkeitsarbeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, A01 Grundlagen Invasiven Rechnens
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, A04 Charakterisierung und Analyse Invasiver Algorithmen zur Entwurfszeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, B02 Invasive eng gekoppelte Prozessorfelder
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, B05 Invasive NoCs - autonome, selbst-optimierende Kommunikations-infrastrukturen für eingebettete Mehrprozessor-Systeme
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C01 Invasives Laufzeitunterstützungssystem (iRTSS)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C02 Simulation invasiver Anwendungen und invasiver Architekturen
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C03 Übersetzung und Code-Erzeugung für Invasive Programme
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C05 IT-Sicherhit bei invasivem Rechnen
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, Z01 Zentrale Dienste und Öffentlichkeitsarbeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, Z02 Validierung und Demonstrator


Publications (Download BibTeX)

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Gangadharan, D., Teich, J., & Chakraborty, S. (2014). Quality-aware video decoding on thermally-constrained MPSoC platforms. In Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 256-263). Zurich, CH: Institute of Electrical and Electronics Engineers Inc..
Roloff, S., Weichslgartner, A., Heißwolf, J., Hannig, F., & Teich, J. (2013). NoC Simulation in Heterogeneous Architectures for PGAS Programming Model. In Proc. 16th International Workshop on Software and Compilers for Embedded Systems (pp. 77-85). St. Goar, DE: New York, NY, USA: ACM Press.
Roloff, S., Hannig, F., & Teich, J. (2012). Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs. In Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 187-192). Sydney, AU: New York, NY, USA: IEEE Press.
Roloff, S., Hannig, F., & Teich, J. (2012). Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation. In Proc. of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (pp. 52-61). Schloss Rheinfels, St. Goar, DE: New York, NY, USA: ACM Press.
Gerndt, M., Hannig, F., Herkersdorf, A., Hollmann, A., Meyer, M., Roloff, S.,... Zaib, A. (2012). An Integrated Simulation Framework for Invasive Computing. In Proc. of the Forum on Specification & Design Languages (FDL) (pp. 185-192). Vienna, AT: New York, NY, USA: IEEE Press.
Roloff, S., Hannig, F., & Teich, J. (2012). Simulation of Resource-Aware Applications on Heterogeneous Architectures. In Proc. of the 8th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (pp. 127-130). Fiuggi, IT: Ghent, Belgium: Academia Press.
Hannig, F., Roloff, S., Snelting, G., Teich, J., & Zwinkau, A. (2011). Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10. In Proceedings of the 14th International Workshop on Software and Compilers for Embedded Systems (pp. 48-55). St. Goar, DE: New York, NY, USA: ACM.


Publications in addition (Download BibTeX)


Sousa, É. (2018). Memory and Interface Architectures for Invasive Tightly Coupled Processor Arrays (Dissertation).
Roloff, S. (2018). Modeling and Simulation of Invasive Applications and Architectures (Dissertation).
Reiche, O., Özkan, M.A., Membarth, R., Teich, J., & Hannig, F. (2017). Generating FPGA-based Image Processing Accelerators with Hipacc. In IEEE (Eds.), Proceedings of the International Conference On Computer Aided Design (pp. 1026-1033). Irvine, US: IEEE.
Reiche, O., Kobylko, C., Hannig, F., & Teich, J. (2017). Auto-vectorization for Image Processing DSLs. In ACM (Eds.), Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) (pp. 21 - 30). Barcelona, ES.
Götzfried, J., Müller, T., Drescher, G., Nürnberger, S., & Backes, M. (2016). RamCrypt: Kernel-based Address Space Encryption for User-mode Processes. In 11th ACM Asia Conference on Computer and Communications Security. Xi'an, China, CN: New York: ACM.
Hannig, F., Lari, V., Boppu, S., Tanase, A.-P., & Reiche, O. (2014). Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Transactions on Embedded Computing Systems, 13(4s), 133:1-133:29. https://dx.doi.org/10.1145/2584660

Last updated on 2019-24-04 at 10:17