Sonderforschungsbereich/Transregio 89 Invasives Rechnen

Adresse:
Cauerstraße 11
91058 Erlangen



Untergeordnete Organisationseinheiten

Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP A01 Grundlagen Invasiven Rechnens
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP A04 Charakterisierung und Analyse Invasiver Algorithmen
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP B02 Invasive eng gekoppelte Prozessorfelder
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C01 Invasives Laufzeitunterstützungssystem (iRTSS)
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C03 Übersetzung und Code-Erzeugung für Invasive Programme
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C05 IT-Sicherheit bei invasivem Rechnen
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP Z02 Valdidierung und Demonstrator
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP Z Zentrale Dienste des SFB/Transregio und Öffentlichkeitsarbeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, A01 Grundlagen Invasiven Rechnens
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, A04 Charakterisierung und Analyse Invasiver Algorithmen zur Entwurfszeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, B02 Invasive eng gekoppelte Prozessorfelder
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, B05 Invasive NoCs - autonome, selbst-optimierende Kommunikations-infrastrukturen für eingebettete Mehrprozessor-Systeme
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C01 Invasives Laufzeitunterstützungssystem (iRTSS)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C02 Simulation invasiver Anwendungen und invasiver Architekturen
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C03 Übersetzung und Code-Erzeugung für Invasive Programme
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C05 IT-Sicherhit bei invasivem Rechnen
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, Z01 Zentrale Dienste und Öffentlichkeitsarbeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, Z02 Validierung und Demonstrator


Publikationen (Download BibTeX)

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Witterauf, M., Tanase, A.-P., Hannig, F., & Teich, J. (2016). Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays. In Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). London, GB.
Roloff, S., Pöppl, A., Schwarzer, T., Wildermann, S., Baader, M., Glaß, M.,... Teich, J. (2016). ActorX10: An Actor Library for X10. In Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10) (pp. 24-29). Santa Barbara, CA, US.
Paul, J., Stechele, W., Oechslein, B., Erhardt, C., Schedel, J., Lohmann, D.,... Henkel, J. (2015). Resource-awareness on heterogeneous MPSoCs for image processing. Journal of Systems Architecture, 61(10), 668-680. https://dx.doi.org/10.1016/j.sysarc.2015.09.002
Witterauf, M., Tanase, A.-P., Teich, J., Lari, V., Zwinkau, A., & Snelting, G. (2015). Adaptive fault tolerance through invasive computing. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (pp. 1-8). Montreal, CA: Institute of Electrical and Electronics Engineers Inc..
Roloff, S., Wildermann, S., Hannig, F., & Teich, J. (2015). Invasive computing for predictable stream processing: A simulation-based case study. Amsterdam, NL: Institute of Electrical and Electronics Engineers Inc..
Lari, V., Tanase, A.-P., Teich, J., Witterauf, M., Khosravi, F., Hannig, F., & Meyer, B. (2015). A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. In Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems (pp. 1-8). Montreal, CA: Institute of Electrical and Electronics Engineers Inc..
Teich, J., Boppu, S., Hannig, F., & Lari, V. (2015). Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays. In Luk, Wayne, Constantinides, George A. (Eds.), Transforming Reconfigurable Systems: A Festschrift Celebrating the 60th Birthday of Professor Peter Cheung (pp. 167-206).
Witterauf, M., Tanase, A.-P., Hannig, F., & Teich, J. (2015). Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing. In Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (pp. 205-208). Fiuggi, IT: HiPEAC.
Tanase, A.-P., Witterauf, M., Teich, J., Hannig, F., & Lari, V. (2015). On-demand fault-tolerant loop processing on massively parallel processor arrays. In In Proceedings of the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 194-201). Toronto, CA: Institute of Electrical and Electronics Engineers Inc..
Tanase, A.-P., Witterauf, M., Hannig, F., & Teich, J. (2015). Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. In Proceedings of the 13th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE) (pp. 188-197). Austin, US: Institute of Electrical and Electronics Engineers Inc..
Gangadharan, D., Sousa, É., Lari, V., Hannig, F., & Teich, J. (2015). Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. In Proceedings of Asilomar Conference on Signals, Systems, and Computers (ASILOMAR) (pp. 398-403). Pacific Grove, CA, US: IEEE Computer Society.
Gangadharan, D., Tanase, A.-P., Hannig, F., & Teich, J. (2014). Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays. Dresden, Germany.
Paul, J., Stechele, W., Sousa, É., Lari, V., Hannig, F., Teich, J.,... Asfour, T. (2014). Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor. In Proc. of the Conference on Design and Architectures for Signal and Image Processing (DASIP) (pp. 1-6). Madrid, ES: Gières, France: ECSI Media.
Gangadharan, D., Teich, J., & Chakraborty, S. (2014). Quality-aware video decoding on thermally-constrained MPSoC platforms. In Proceedings of the 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) (pp. 256-263). Zurich, CH: Institute of Electrical and Electronics Engineers Inc..
Weichslgartner, A., Gangadharan, D., Wildermann, S., Glaß, M., & Teich, J. (2014). DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014) (pp. 10). New Delhi, IN: Association for Computing Machinery, Inc.
Glocker, E., Boppu, S., Chen, Q., Schlichtmann, U., Teich, J., & Schmitt-Landsiedel, D. (2014). Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs). Advances in Radio Science, 12, 103-109. https://dx.doi.org/10.5194/ars-12-103-2014
Roloff, S., Hannig, F., & Teich, J. (2014). Towards Actor-oriented Programming on PGAS-based Multicore Architectures. In Proc. of the first International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS) (pp. 1-2). Lübeck, DE.
Sousa, É., Gangadharan, D., Hannig, F., & Teich, J. (2014). Runtime reconfigurable bus arbitration for concurrent applications on heterogeneous MPSoC architectures. In Proceedings of the EUROMICRO Digital System Design Conference (DSD) (pp. 74-81). Verona, IT: Institute of Electrical and Electronics Engineers Inc..
Roloff, S., Weichslgartner, A., Heißwolf, J., Hannig, F., & Teich, J. (2013). NoC Simulation in Heterogeneous Architectures for PGAS Programming Model. In Proc. 16th International Workshop on Software and Compilers for Embedded Systems (pp. 77-85). St. Goar, DE: New York, NY, USA: ACM Press.
Roloff, S., Hannig, F., & Teich, J. (2012). Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation. In Proc. of the 15th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (pp. 52-61). Schloss Rheinfels, St. Goar, DE: New York, NY, USA: ACM Press.


Zusätzliche Publikationen (Download BibTeX)


Sousa, É. (2018). Memory and Interface Architectures for Invasive Tightly Coupled Processor Arrays (Dissertation).
Roloff, S. (2018). Modeling and Simulation of Invasive Applications and Architectures (Dissertation).
Reiche, O., Özkan, M.A., Membarth, R., Teich, J., & Hannig, F. (2017). Generating FPGA-based Image Processing Accelerators with Hipacc. In IEEE (Eds.), Proceedings of the International Conference On Computer Aided Design (pp. 1026-1033). Irvine, US: IEEE.
Reiche, O., Kobylko, C., Hannig, F., & Teich, J. (2017). Auto-vectorization for Image Processing DSLs. In ACM (Eds.), Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) (pp. 21 - 30). Barcelona, ES.
Götzfried, J., Müller, T., Drescher, G., Nürnberger, S., & Backes, M. (2016). RamCrypt: Kernel-based Address Space Encryption for User-mode Processes. In 11th ACM Asia Conference on Computer and Communications Security. Xi'an, China, CN: New York: ACM.
Hannig, F., Lari, V., Boppu, S., Tanase, A.-P., & Reiche, O. (2014). Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Transactions on Embedded Computing Systems, 13(4s), 133:1-133:29. https://dx.doi.org/10.1145/2584660

Zuletzt aktualisiert 2018-19-12 um 22:51