Sonderforschungsbereich/Transregio 89 Invasives Rechnen

Address:
Cauerstraße 11
91058 Erlangen



Subordinate Organisational Units

Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP A01 Grundlagen Invasiven Rechnens
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP A04 Charakterisierung und Analyse Invasiver Algorithmen
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP B02 Invasive eng gekoppelte Prozessorfelder
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C01 Invasives Laufzeitunterstützungssystem (iRTSS)
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C03 Übersetzung und Code-Erzeugung für Invasive Programme
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C05 IT-Sicherheit bei invasivem Rechnen
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP Z02 Valdidierung und Demonstrator
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP Z Zentrale Dienste des SFB/Transregio und Öffentlichkeitsarbeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, A01 Grundlagen Invasiven Rechnens
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, A04 Charakterisierung und Analyse Invasiver Algorithmen zur Entwurfszeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, B02 Invasive eng gekoppelte Prozessorfelder
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, B05 Invasive NoCs - autonome, selbst-optimierende Kommunikations-infrastrukturen für eingebettete Mehrprozessor-Systeme
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C01 Invasives Laufzeitunterstützungssystem (iRTSS)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C02 Simulation invasiver Anwendungen und invasiver Architekturen
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C03 Übersetzung und Code-Erzeugung für Invasive Programme
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C05 IT-Sicherhit bei invasivem Rechnen
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, Z01 Zentrale Dienste und Öffentlichkeitsarbeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, Z02 Validierung und Demonstrator


Publications (Download BibTeX)

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Smirnov, F., Reimann, F., Teich, J., Han, Z., & Glaß, M. (2018). Automatic Optimization of Redundant Message Routings in Automotive Networks. In ACM (Eds.), Proceedings of 21st International Workshop on Software and Compilers for Embedded Systems (SCOPES 2018). Sankt Goar, DE.
Mattauch, S., Lohmann, K., Hannig, F., Lohmann, D., & Teich, J. (2018). The Gender Gap in Computer Science --- A Bibliometric Analysis.
Sousa, É., Witterauf, M., Brand, M., Tanase, A.-P., Hannig, F., & Teich, J. (2018). Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. Milan, Italy.
Pourmohseni, B., Wildermann, S., Glaß, M., & Teich, J. (2017). Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems. Grenoble, FR.
Brand, M., Hannig, F., Tanase, A.-P., & Teich, J. (2017, July). Efficiency in ILP Processing by Using Orthogonality. Poster presentation at The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017), Seattle, US.
Sousa, É., Chakraborty, A., Tanase, A.-P., Hannig, F., & Teich, J. (2017). TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays. Poster presentation at Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, MX.
Brand, M., Hannig, F., Tanase, A.-P., & Teich, J. (2017). Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. In 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (pp. 5-12). Korea University, Seoul, Korea, KR.
Roloff, S., Hannig, F., & Teich, J. (2017). High Performance Network-on-Chip Simulation by Interval-based Timing Predictions. In ACM (Eds.), Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) (pp. 2-11). Seoul, Republic of Korea, KR.
Zaib, A., Heisswolf, J., Weichslgartner, A., Wild, T., Teich, J., Becker, J., & Herkersdorf, A. (2017). Efficient Task Spawning for Shared Memory and Message Passing in Many-core Architectures. Journal of Systems Architecture, 77, 72-82. https://dx.doi.org/10.1016/j.sysarc.2017.03.004
Witterauf, M., Tanase, A.-P., Hannig, F., & Teich, J. (2016). Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays. In Proceedings of the 27th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). London, GB.
Weichslgartner, A., Wildermann, S., Götzfried, J., Freiling, F., Glaß, M., & Teich, J. (2016). Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. In In Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (pp. 153-162). St. Goar, DE.
Roloff, S., Pöppl, A., Schwarzer, T., Wildermann, S., Baader, M., Glaß, M.,... Teich, J. (2016). ActorX10: An Actor Library for X10. In Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10) (pp. 24-29). Santa Barbara, CA, US.
Teich, J., Glaß, M., Roloff, S., Schröder-Preikschat, W., Snelting, G., Weichslgartner, A., & Wildermann, S. (2016). Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution using Invasive Computing. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16) (pp. 313-320). Lyon, FR.
Fickenscher, J., Reiche, O., Schlumberger, J., Hannig, F., & Teich, J. (2016). Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs. In Proceedings of the 18th IEEE International High-Level Design Validation and Test Workshop (HLDVT) (pp. 70-77). Santa Cruz, CA, US.
Lari, V. (2016). Invasive Tightly Coupled Processor Arrays. In Springer book series on Computer Architecture and Design Methodologies Singapore: Springer.
Lari, V., Weichslgartner, A., Tanase, A.-P., Witterauf, M., Khosravi, F., Teich, J.,... Becker, J. (2016). Providing Fault Tolerance Through Invasive Computing. it - Information Technology, 58(6), 309-238.
Drescher, G., Erhardt, C., Freiling, F., Götzfried, J., Lohmann, D., Maene, P.,... Wildermann, S. (2016). Providing security on demand using invasive computing. it - Information Technology, 58(6), 281-295. https://dx.doi.org/10.1515/itit-2016-0032
Würstlein, A., Gernoth, M., Götzfried, J., & Müller, T. (2016). Exzess: Hardware-based RAM encryption against physical memory disclosure. (pp. 60-71). Springer Verlag.
Roloff, S., Wildermann, S., Hannig, F., & Teich, J. (2015). Invasive computing for predictable stream processing: A simulation-based case study. Amsterdam, NL: Institute of Electrical and Electronics Engineers Inc..
Witterauf, M., Tanase, A.-P., Hannig, F., & Teich, J. (2015). Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing. In Proceedings of the 11th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) (pp. 205-208). Fiuggi, IT: HiPEAC.

Last updated on 2017-07-12 at 01:00