Sonderforschungsbereich/Transregio 89 Invasives Rechnen

Address:
Cauerstraße 11
91058 Erlangen



Subordinate Organisational Units

Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP A01 Grundlagen Invasiven Rechnens
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP A04 Charakterisierung und Analyse Invasiver Algorithmen
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP B02 Invasive eng gekoppelte Prozessorfelder
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C01 Invasives Laufzeitunterstützungssystem (iRTSS)
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C03 Übersetzung und Code-Erzeugung für Invasive Programme
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP C05 IT-Sicherheit bei invasivem Rechnen
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP Z02 Valdidierung und Demonstrator
Sonderforschungsbereich/Transregio 89/3 Invasives Rechnen, TP Z Zentrale Dienste des SFB/Transregio und Öffentlichkeitsarbeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, A01 Grundlagen Invasiven Rechnens
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, A04 Charakterisierung und Analyse Invasiver Algorithmen zur Entwurfszeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, B02 Invasive eng gekoppelte Prozessorfelder
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, B05 Invasive NoCs - autonome, selbst-optimierende Kommunikations-infrastrukturen für eingebettete Mehrprozessor-Systeme
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C01 Invasives Laufzeitunterstützungssystem (iRTSS)
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C02 Simulation invasiver Anwendungen und invasiver Architekturen
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C03 Übersetzung und Code-Erzeugung für Invasive Programme
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, C05 IT-Sicherhit bei invasivem Rechnen
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, Z01 Zentrale Dienste und Öffentlichkeitsarbeit
Sonderforschungsbereich/Transregio 89 Invasives Rechnen, Z02 Validierung und Demonstrator


Publications (Download BibTeX)

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Pourmohseni, B., Smirnov, F., Khdr, H., Wildermann, S., Teich, J., & Henkel, J. (2019). Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems. In Proceedings of the 40th IEEE Real-Time Systems Symposium (RTSS) (pp. 1-13). Hong Kong, CN.
Palutke, R., Neubaum, A., & Götzfried, J. (2019). SEVGuard: Protecting User Mode Applications using Secure Encrypted Virtualization. In SecureComm 2019 Proceedings. Orlando, US: New York City, United States of America: Springer.
Heidorn, C., Witterauf, M., Hannig, F., & Teich, J. (2019). Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. Journal of Computers, 14(8), 541-556. https://dx.doi.org/10.17706/jcp.14.8.541-556
Pourmohseni, B., Smirnov, F., Wildermann, S., & Teich, J. (2019). Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. In Proceedings of the 31th Euromicro Conference on Real-Time Systems (ECRTS) (pp. 12:1--12:24). Stuttgart, Germany.
Roloff, S., Hannig, F., & Teich, J. (2019). Modeling and Simulation of Invasive Applications and Architectures. Singapore: Springer.
Brand, M., Witterauf, M., Sousa, É., Tanase, A.-P., Hannig, F., & Teich, J. (2019). *-Predictable MPSoC Execution of Real-Time Control Applications Using Invasive Computing. Concurrency and Computation-Practice & Experience. https://dx.doi.org/10.1002/cpe.5149
Pourmohseni, B., Wildermann, S., Glaß, M., & Teich, J. (2019). Hard Real-Time Application Mapping Reconfiguration for NoC-Based Many-Core Systems. Real-Time Systems, 1-37. https://dx.doi.org/10.1007/s11241-019-09326-y
Brand, M., Witterauf, M., Hannig, F., & Teich, J. (2019). Anytime Instructions for Programmable Accuracy Floating-Point Arithmetic. In ACM (Eds.), Proceedings of the ACM International Conference on Computing Frontiers 2019 (pp. 215 - 219). Alghero, Sardinia, IT.
Streit, F.-J., Letras, M., Wildermann, S., Hackenberg, B., Falk, J., Becher, A., & Teich, J. (2018). Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. In IEEE-Xplore digital library. Cancun, MX.
Smirnov, F., Reimann, F., Teich, J., Han, Z., & Glaß, M. (2018). Automatic Optimization of Redundant Message Routings in Automotive Networks. In ACM (Eds.), Proceedings of 21st International Workshop on Software and Compilers for Embedded Systems (SCOPES 2018). Sankt Goar, DE.
Sousa, É., Witterauf, M., Brand, M., Tanase, A.-P., Hannig, F., & Teich, J. (2018). Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. In Proceedings of the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). Milan, Italy.
Mattauch, S., Lohmann, K., Hannig, F., Lohmann, D., & Teich, J. (2018). The Gender Gap in Computer Science --- A Bibliometric Analysis.
Weichslgartner, A., Wildermann, S., Gangadharan, D., Glaß, M., & Teich, J. (2018). A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. ACM Transactions on Embedded Computing Systems.
Pourmohseni, B., Wildermann, S., Glaß, M., & Teich, J. (2017). Predictable Run-Time Mapping Reconfiguration for Real-Time Applications on Many-Core Systems. In Proceedings of the 25th International Conference on Real-Time Networks and Systems (RTNS). Grenoble, FR.
Brand, M., Hannig, F., Tanase, A.-P., & Teich, J. (2017, July). Efficiency in ILP Processing by Using Orthogonality. Poster presentation at The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017), Seattle, US.
Sousa, É., Chakraborty, A., Tanase, A.-P., Hannig, F., & Teich, J. (2017). TCPA Editor: A Design Automation Environment for a Class of Coarse-Grained Reconfigurable Arrays. Poster presentation at Demo Night at the IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, MX.
Brand, M., Hannig, F., Tanase, A.-P., & Teich, J. (2017). Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. In 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (pp. 5-12). Korea University, Seoul, Korea, KR.
Roloff, S., Hannig, F., & Teich, J. (2017). High Performance Network-on-Chip Simulation by Interval-based Timing Predictions. In ACM (Eds.), Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia) (pp. 2-11). Seoul, Republic of Korea, KR.
Zaib, A., Heisswolf, J., Weichslgartner, A., Wild, T., Teich, J., Becker, J., & Herkersdorf, A. (2017). Efficient Task Spawning for Shared Memory and Message Passing in Many-core Architectures. Journal of Systems Architecture, 77, 72-82. https://dx.doi.org/10.1016/j.sysarc.2017.03.004
Roloff, S., Pöppl, A., Schwarzer, T., Wildermann, S., Baader, M., Glaß, M.,... Teich, J. (2016). ActorX10: An Actor Library for X10. In Proceedings of the 6th ACM SIGPLAN X10 Workshop (X10) (pp. 24-29). Santa Barbara, CA, US.


Publications in addition (Download BibTeX)


Sousa, É. (2018). Memory and Interface Architectures for Invasive Tightly Coupled Processor Arrays (Dissertation).
Roloff, S. (2018). Modeling and Simulation of Invasive Applications and Architectures (Dissertation).
Reiche, O., Özkan, M.A., Membarth, R., Teich, J., & Hannig, F. (2017). Generating FPGA-based Image Processing Accelerators with Hipacc. In IEEE (Eds.), Proceedings of the International Conference On Computer Aided Design (pp. 1026-1033). Irvine, US: IEEE.
Reiche, O., Kobylko, C., Hannig, F., & Teich, J. (2017). Auto-vectorization for Image Processing DSLs. In ACM (Eds.), Proceedings of the 18th International Conference on Languages, Compilers, Tools, and Theory for Embedded Systems (LCTES) (pp. 21 - 30). Barcelona, ES.
Götzfried, J., Müller, T., Drescher, G., Nürnberger, S., & Backes, M. (2016). RamCrypt: Kernel-based Address Space Encryption for User-mode Processes. In 11th ACM Asia Conference on Computer and Communications Security. Xi'an, China, CN: New York: ACM.
Hannig, F., Lari, V., Boppu, S., Tanase, A.-P., & Reiche, O. (2014). Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Transactions on Embedded Computing Systems, 13(4s), 133:1-133:29. https://dx.doi.org/10.1145/2584660

Last updated on 2019-24-04 at 10:17