Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing - Ramaswami, Arjun; Kenter, Tobias; Kühne, Thomas D.; Plessl, Christian (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2021)
The 3D Fast Fourier Transformation (3D FFT) is a critical routine in a number of applications of today’s HPC workloads. Optimising it for computational performance with the use of FPGAs has been a focus of several studies. However, a systematic study has been missing on the viability of different scenarios how FPGA-accelerated 3D FFT implementations can be integrated into real world applications originally implemented on high-end CPUs. In this paper, we address this with two scenarios for offloading 3D FFT computations to an FPGA and investigate their feasibility in comparison to highly optimised FFTW based executions on CPU in terms of computation time and power consumption. In the first scenario, performance of individual 3D FFT offloading to FPGA is found to be limited by latency and unidirectional bandwidth of PCIe data transfers. This bottleneck is overcome in the second scenario by overlapping in a batched mode data transfers and computations in the FPGA to find performance competitive to CPU. In both these scenarios, projections to next generation PCIe connections show additional potential for the FPGA with up to 2x speedup over CPU executions. Furthermore, measurements indicate 3.7x to 4.1x lower average power consumption on the FPGA.
CRIS-Team Scopus Importer:2023-03-20
Keywords: 3D FFT; FPGA; HPC; OpenCL