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@article{faucris.121332684,
abstract = {In this paper, we present a novel methodology to calculate the Arithmetic Error Rate (AER) for deterministic approximate adder architectures where the calculation of each output bit is restricted to a subset of the input bits, denoted as visibilities. Such architectures have been widely proposed in the literature and are, e.g., obtained when splitting the carry chain in a carry-propagate adder into partitions each computed by a separate parallel adder, or when removing carry-lookahead operators in a parallel prefix adder. Our contribution is a unified calculus for determining the arithmetic error rate for (a) such deterministic approximate adder architectures making use of visibilities and (b) the general case of arbitrarily (also non-uniformly) distributed input bits.},
author = {Echavarria Gutiérrez, Jorge Alfonso and Wildermann, Stefan and Potwigin, Eduard and Teich, Jürgen},
doi = {10.1109/LES.2017.2760922},
faupublication = {yes},
journal = {IEEE Embedded Systems Letters},
keywords = {Approximate Adders; Arithmetic Error Rate; Approximate Computing},
peerreviewed = {Yes},
title = {{Efficient} {Arithmetic} {Error} {Rate} {Calculus} for {Visibility} {Reduced} {Approximate} {Adders}},
year = {2017}
}