A Novel Approach to Entirely Integrate Virtual Test into Test Development Flow - Lu, Ping; Glaser, Daniel; Uygur, Gürkan; Helmreich, Klaus (Proceedings, 2009)
In this paper, we present an open architecture Virtual Test Environment (VTE) which can be easily integrated into various modularized Automatic Test Systems (ATS) compliant to Open Standard Architecture (OSA). The focus of this paper is to analyze and address the major issues that still prevent the application of Virtual Test (VT) from day-to-day's practice. As a pilot demonstration, a VHDLAMS based VTE is established and an ADC test is performed. The environment is intended to seamlessly interoperate with the test system during test program development procedure. © 2009 EDAA.
UnivIS-Import:2015-04-16:Pub.2009.tech.IE.c3scha.anovel
Keywords: ATML; Hardware description language; IEEE1641; Simulation; Test generation; VHDL; Virtual Test