43 Gb/s CP-QPSK Realtime Receiver Demonstrator based on FPGAs and Block Processing - Geyer, J.C.; Fludger, C.R.S.; Duthel, T.; Presslein, P.; Schulien, C.; Schmauß, Bernhard (ECOC 2009, Vienna, Austria, 20-24 September, 2009)
We present measurement results of an FPGA-based 43Gb/s Realtime Coherent Receiver Demonstrator. Due to limitations we use block-aggregation and process 1/32 of the input data stream. We show back-to-back performance and chromatic dispersion tolerance.
UnivIS-Import:2015-04-16:Pub.2009.tech.IE.LEH.43gbsc