A combined space-time multiplex architecture for a stacked smart sensor chip - Loos, Andreas; Schmidt, Michael; Fey, Dietmar; et al. (Proc. SPIE, Vol. 6185 / Computer Architectures and Photonic Interconnects, 2006)
We present a fine-grain parallel processor architecture which considers particularly the requirements defined by future 3-dimensional (3D) stacked optoelectronic devices. The architecture concept is well-suited for novel detector arrays which are exploited in data communication applications based on high-speed VCSEL photonic interconnects as well as for optical sensing applications in smart CMOS camera chips. We assume the presence of a two-dimensional optoelectronic interface mounted on top of the stacked device. Such a vertical communication scheme is perfect for the realization of very compact and fast working devices in embedded systems, e.g. in gripper arms of robots.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.IMMD3.acombi_2
Keywords: Intelligent optoelectronic CMOS sensor systems; Opto-ASICs; Parallel computation