An Advanced Concept for Coherent Ultra-Low Phase-Noise Clock, LO and Trigger Generation & Distribution in 6G Massive-MIMO Systems - Scheder, André; Witte, Lukas; Rottinghaus, Jonas; Gröschel, Patrick; Karle, Christian; Neu, Marc; Nuss, Benjamin; Vossiek, Martin (2024 54th European Microwave Conference (EuMC), 2024)
The current development of the 6G mobile communications standard shows that in addition to an increase in data rate, a reduction in latency and completely new functionalities such as joint-communication and sensing (JCAS) could become an integral part of the standard. One approach to achieving these goals is massive multiple-input multiple-output (MIMO) systems, whereby both higher energy and bandwidth efficiency can be achieved per device and the entire system itself becomes more resilient. With regard to JCAS, the high number of channels enables a more precise position estimation of the objects to be detected. At the same time, the extremely high number of channels also enforces new requirements for the hardware, as, for example, all channels must be phase-coherent and synchronous. This requirement extends from the clock signal for the digital-to-analog and analog-to-digital converters, to the local oscillators for the mixers, to the trigger signal, which ensures that all system components start at the same time. The backplane system presented in this paper supplies all signals required for the phase-coherent operation of a massive MIMO system while simultaneously achieving ultra-low phase noise even across several master-slave modules.
CRIS-Team Scopus Importer:2024-12-13
Keywords: 6G mobile communication; Phase noise; Local oscillators; System testing; Spectral efficiency; Backplanes; Massive MIMO; Synchronization; Standards; Clocks; 6G; massive MIMO; clock distribution; phase coherency

Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G Development - Karle, Christian; Neu, Marc; Nuss, Benjamin; Chen, Jiayi; Witte, Lukas; Scheder, André; Harbaum, Tanja; Becker, Jurgen (2024 IEEE 37th International System-on-Chip Conference (SOCC), 2024)
Compared to 5th generation (5G), 6G is expected to offer latencies below 1 ms, higher data rates in the range of multiple Gbit/s, and enable the use of new frequency bands and application fields such as joint-communication and sensing (JCAS). For the development of the new mobile standard, research, and industry are increasingly relying on the use of high-performance multiple-input multiple-output (MIMO)-capable software-defined radio (SDR) systems. However, existing systems are often limited in their applicability due to bandwidth, frequency, and performance limitations by manufacturer-specific hardware. To overcome these limitations, we present a modular hardware design for a high-performance MIMO-capable SDR system. We enable the exchange of the digital processing unit, the replacement, or configuration of the analog IF front ends, and the configurability of the clock distribution network. Therefore, our system achieves high adaptability compared to manufacture-specific systems. To match the changing requirements in 6G, our modular SDR system bypasses the time-consuming and costly hardware design process and accelerates the overall development. Finally, we demonstrate the performance of our modular SDR system by implementing a high-performance orthogonal frequency-division multiplexing (OFDM) radar, which requires high sampling and data rates processed in real-time. Based on our high-performance example application, our modular SDR system matches the performance of fixed-structure SDR systems, required for 6G.
CRIS-Team Scopus Importer:2024-12-13
Keywords: 6G; modular hardware design; RFSoC; SDR system

Scalable Multi-Level Synchronization Technique of Distributed Multi-RFSoC-Server Systems for 6G - Karle, Christian; Neu, Marc; Nuss, Benjamin; Witte, Lukas; Scheder, André; Waldner, Eva; Shkurtaj, Ema; Harbaum, Tanja; Becker, Jurgen (International System on Chip Conference, 2024)
The new 6th generation (6G) standard promises increased data transmission rates and opens up entirely new application fields, such as joint-communication and sensing (JCAS). Modern high-performance multiple-input multiple-output (MIMO) systems with high bandwidth and channel count allow evaluation and testing of waveforms and algorithms in real-world scenarios. However, commercial off-the-shelf (COTS) MIMO systems are often costly and cannot be scaled to massive MIMO (mMIMO) systems without huge overhead. The ReLoDAQ system, based on combined radio frequency system-on-chip (RFSoC)-server architecture, offers a cost-effective and scalable solution for the development of a modern mMIMO system. However, this system is only scalable in terms of channel count and does not provide scalable synchronization and trigger mechanisms, which are essential for applications like JCAS or radar. In this paper, we present a scalable sample- and data-level synchronization and trigger mechanism to operate a mMIMO system based on the ReLoDAQ structure in a phase coherent manner. To achieve this, we extend the firmware of the RFSoCs with additional trigger and synchronization logic. Furthermore, we developed a scalable clock distribution network to distribute phase coherent clocks in the mMIMO system. Through measurements on an experimental mMIMO system consisting of two RFSoCs and four servers, we demonstrate that our approach enables phase coherent operation across all channels in the mMIMO system based on the cost-efficient and scalable ReLoDAQ architecture.
CRIS-Team Scopus Importer:2024-12-13
Keywords: 6G; clock distribution; mMIMO; RFSoC; synchronization