A 15-Gb/s PMCW Radar PRBS-Generator for MIMO and Joint Radar-Communication Systems - Probst, Florian; Engelmann, Andre; Hetterle, Philip; Issakov, Vadim; Weigel, Robert; Dietz, Marco (2022 Asia-Pacific Microwave Conference, 2022)
This paper presents an integrated baseband pseudo-random noise generator at 15 Gb/s for phase-modulated continuous-wave (PMCW) radar systems. Through slow-time modulating an outer code (OC) onto a pseudo-random binary sequence (PRBS), the circuit enables MIMO and joint radar-communication (RadCom) systems in the D-Band and above. To the best of the authors’ knowledge, this has not yet been demonstrated. The mixed-signal circuit consumes 7.2mW in power and 400 × 530μm2 in area. It was realized in a 22nm fully-depleted silicon on insulator (FDSOI) technology, where the PRBS is generated by a shift register formed by true single-phaseclock (TSPC) flip-flops.<br
Keywords: MIMO radar; phase-modulated continuouswave (PMCW); radar-communication (RadCom); true singlephase-clock (TSPC).

A 1.7 dBm OP1dB D-Band Up-Conversion Mixer Utilizing Adaptive Back-Gate Bias in 22 nm FDSOI - Huang, Tianzhu; Hetterle, Philip; Engelmann, Andre; Probst, Florian; Schrotz, Albert-Marcel; Weigel, Robert; Fischer, Georg (2024 Asia-Pacific Microwave Conference, 2024)

A 21 GHz Bandwidth 30 dB Gain VGA for 6G Basband Systems in 22 nm FDSOI - Hetterle, Philip; Engelmann, Andre; Scheller, Kai; Huang, Tianzhu; Weigel, Robert; Franchi, Norman (German Microwave Conference (GEMIC), 2025)
This paper presents a 5-stage wideband variable gain amplifier (VGA) integrated in 22 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The circuit comprises three different core circuit topologies, composed by an input buffer, three gain control stages and a high-power ouput stage. The VGA achieves 30 dB gain with a power consumption of 44 mW, exhibiting a continuous tuning range of 33 dB, covering a 3 dB bandwidth of 21 GHz, while occupying a area of 0.077 mm2. The VGA is optimized for operation within high-data rate 6G receiver system
Keywords: CMOS; FDSOI; VGA; baseband; low voltage; mobile communication; IC; 6G.

A 34 GHz CMOS VCO with Transformer Tail-Node Filter and TSPC Frequency Divider in 22 nm FDSOI - Engelmann, Andre; Probst, Florian; Hetterle, Philip; Weigel, Robert (2024 IEEE Radio and Wireless Week, RWW 2024 - 2024 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2024, 2024)
This work proposes a compact, low-power CMOS voltage-controlled oscillator (VCO) with distributed transformer tail-node filter for phase noise reduction. The circuit is integrated into a 22 nm fully-depleted silicon-on-insulator (FDSOI) technology, offering high-performance n- and p-MOS transistors. Using a combination of SOI varactors and switched capacitors, a wide tuning range of 22.8%, covering 30.4 to 38.24 GHz, is reached while maintaining a phase noise below -97 dBc/Hz at a 1 MHz carrier offset. An area- and power-efficient true single-phase-clock (TSPC) frequency divider is implemented to ease the use of the VCO within a low-frequency PLL. The overall circuit consumes 9.4 mW supplied from a 0.8 V source and 170 370 m2 core area, including an output buffer and the divider. The circuit performance results in a corresponding FOM and FOMT of -178.3 and -185.3 dBc/Hz.
CRIS-Team Scopus Importer:2024-03-15
Keywords: CMOS; Cross-coupled VCO; FDSOI; frequency divider; low phase-noise; oscillator; signal generation; tail filter

A 3-Stacked 10.2 dBm OP1dB D-Band Power Amplifier in 22 nm FDSOI for 6G Communication - Huang, Tianzhu; Engelmann, Andre; Hetterle, Philip; Probst, Florian; Weigel, Robert (2023 Asia-Pacific Microwave Conference, 2023)
This paper proposes a high-linearity 3-stacked D-band power amplifier (PA) for 6G communication. The PA is fabricated in 22 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology and consists of four stages, including three driver stages. The capacitive neutralization approach is adopted in all stages for gain-boosting. Transistor stacking is applied in the output stage for high output power and linearity. The circuit achieves a peak power gain of 23.8 dB at 135 GHz with a 3-dB bandwidth of 16 GHz. A maximum measured output power of 13 dBm, an output referred 1-dB compression point OP1dB of 10.2 dBm, and a peak power-added efficiency (PAE) of 9.9% are attained, while occupying only 0.081 mm² of chip are
Keywords: CMOS; D-band; FDSOI; high linearity; mm-wave; power amplifier (PA); stacked amplifier; 6G

A Broadband Sub-THz Push-Push Frequency Doubler in 22 nm FDSOI - Scheller, Kai; Engelmann, Andre; Hetterle, Philip; Weigel, Robert; Schrotz, Albert-Marcel; Fischer, Georg (IEEE MTT-S Latin America Microwave Conference (LAMC-2025), 2025)
This paper presents a sub-THz push-push frequency doubler with a D-band power amplifier (PA) chain demonstrated in a 22 nm fully-depleted silicon-on-insulator (FDSOI) technology. The D-band PA comprises three common-source (CS) driver stages and a high-power stacked output stage. The amplifier stages utilize the capacitive neutralization technique for gain-boosting. Two parallel push-push doubler stages are employed after the PA. The input power distribution and matching to the PA optimum load-pull point are achieved by leveraging an area-efficient stacked transformer with two secondary coils. The overall circuitry occupies a compact core area of 0.0625 mm2. The PA and frequency doubler attains a maximal gain of 7 dB and a saturated output power Psat of -5 dBm, covering a 60 GHz 3 dB-bandwidth. Furthermore, the circuits exhibits a minimum suppression of 35 dBc to the fundamental frequency. The circuit’s DC-power consumption is below 230 mW, supplied by 1.6 V and 0.8 V.<br
Keywords: CMOS; FDSOI; frequency doubler; sub-THz; transformer

A Compact Energy-Saving D-Band Frequency Quadrupler with -1 dB Conversion Gain in 22 nm FDSOI - Engelmann, Andre; Probst, Florian; Hetterle, Philip; Weigel, Robert (2023 Asia-Pacific Microwave Conference (APMC), 2023)
This work presents a compact and energy-saving D-band frequency multiplier by 4 (quadrupler) integrated into an advanced 22 nm fully-depleted silicon-on-insulator (FDSOI) technology. The circuit consists of a multi-phase driven two-stage push-push doubler architecture achieving a conversion gain of -1 dB and covers a bandwidth of 23 GHz centered at 133 GHz. At 0.8 V supply voltage, the quadrupler attains a maximum output power of -3.4 dBm and an efficiency of 1.71% while consuming only 27 mW of DC power. A harmonic rejection greater than 26 dBc is reached over the entire bandwidth. The core cell of the circuit occupies a compact chip area of 325 × 250 μm2
CRIS-Team Scopus Importer:2024-12-16
Keywords: CMOS; D-band; FDSOI; frequency multiplier; MMIC; quadrupler; signal generation

A Design-for-Sensitivity Strategy for Charge-Pump-Based Receivers - Schumacher, Tim; Fath, Patrick; Schmickl, Stefan; Faseth, Thomas; Hetterle, Philip; Weigel, Robert; Pretl, Harald (Proceedings - 2020 Austrochip Workshop on Microelectronics, Austrochip 2020, 2020)
This work presents the theoretical fundamentals of designing charge-pump-based receivers for maximum open-circuit voltage sensitivity (OCVS). From a classical Dickson charge pump with sub-zero-V_th transistors, various models are derived to extract correlation between specific parameters (e.g. number of stages, transistor widths and capacitor sizes) and the output voltage, maximum data rate and input impedance. This approach enabled us to develop an easily applied design strategy for this type of low-power receivers, which we demonstrate here for the 868MHz and 915MHz short-range-devices bands. It also considers an external matching network, our design strategy provides flexibility in layout generation and allows fast designing of receivers. Our strategy focuses on a rapid design flow rather than accurate representation, and is demonstrated using the example of a receiver design. In addition, the limitations of the derivations are discussed, and further optimizations are suggested.
CRIS-Team Scopus Importer:2020-12-04
Keywords: Charge-pump; design-Automation; matching; passive; receiver; SRD; wake-up

A Low-Voltage Broadband D-Band BPSK Modulator for a PMCW Radar Transmitter in 22 nm FDSOI - Engelmann, Andre; Probst, Florian; Hetterle, Philip; Weigel, Robert; Dietz, Marco (Asia-Pacific Microwave Conference 2022 (APMC), 2022)
This work presents a broadband low-voltage binary-phase-shift-keying (BPSK) modulator operating in the D-band. The modulator is intended for a phase-modulated continuous-wave (PMCW) radar transmitter with a chip rate of up to 12.5 Gb/s and integrated into an advanced 22 nm fully-depleted silicon-on-insulator (FDSOI) technology. The circuit covers a bandwidth of 34 GHz at a carrier frequency of 140 GHz with a maximum conversion gain of 2.5 dB. A 1 dB output compression point of −7.2 dBm is reached while consuming 27 mW DC-Power at a supply voltage of only 0.8 V and a circuit core area of 0.051 sqm
Keywords: Binary-phase-shift-keying (BPSK) modulator; CMOS; D-band; FDSOI; MMIC; phase-modulated continuous-wave (PMCW) radar.

A Low Voltage Folded Gilbert Cell Mixer for 6G Communication Systems - Hetterle, Philip; Engelmann, Andre; Probst, Florian; Huang, Tianzhu; Weigel, Robert (Asia-Pacific Microwave Conference (APMC), 2023)
This paper presents the design of a folded Gilbert cell D-band down-conversion mixer manufactured in a 22 nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The mixer runs on a supply voltage of 800 mV and consumes a power of 28 mW. The device achieves a conversion gain of -7 dB while maintaining a broad bandwidth of 30 GH
Keywords: CMOS; D-band; FDSOI; Gilbert cell; down-conversion; low voltage; mixer; mm-wave; mobile communication; 6G

Design of a Low Voltage D-band LNA in 22 nm FDSOI - Hetterle, Philip; Engelmann, Andre; Probst, Florian; Weigel, Robert; Dietz, Marco (17th European Microwave Integrated Circuits Conference (EuMIC), 2022)
This paper presents a low voltage D-band Low Noise Amplifier (LNA) manufactured in a 22nm fully-depleted silicon-on-insulator FDSOI CMOS technology. The circuit consists of 4 differential stages. The first stage is optimized for minimal noise, while the other three are optimized to achieve maximum gain. Therefore, a capacitive neutralization technique is applied. Transmissionline-based matching networks are used to match the stages for a bandwidth of over 20 GHz. The measurement results show a gain of 17 dB while achieving a low noise figure of less than 8 dB at a supply voltage of only 0.8V.<br
Keywords: CMOS; D-band; FDSOI; LNA; mm-wave; mobile communication; 6G

Design of two Low DC-Power High-Efficiency D-Band Power Amplifiers in 22 nm FDSOI - Engelmann, Andre; Hetterle, Philip; Probst, Florian; Weigel, Robert; Dietz, Marco (17th European Microwave Integrated Circuits Conference (EuMIC), 2022)
This paper presents two low DC-power D-band power amplifiers (PAs) integrated into a 22nm fully-depleted silicon-on-insulator (FDSOI) technology. Both amplifiers use the capacitive neutralization technique for gain-boosting and stability enhancement. The design procedure for transformer-based (TB) and line-based (LB) matching networks and the advantages and disadvantages of both architectures are discussed. The PA implementation focuses on low DC-power consumption, high efficiency, and compact device realization. The fabricated TBand LB-PA show high maximum power-added-efficiency (PAE) of 9 and 8% consuming 46 and 52mW respectively at a supply voltage of only 0.8V. The saturated output powers Psat reach 6.8dBm and 6.5dBm while achieving small-signal gains of 24.2 and 23.4 dB with 3-dB-bandwidths of 23 and 26 GHz.<br
Keywords: Power amplifier (PA); D-Band; millimeter-wave; FDSOI; CMOS; phase-modulated continuous-wave (PMCW) radar