ALPACA: An Accelerator Chip for Nested Loop Programs - Walter, Dominik; Brand, Marcel; Heidorn, Christian; Witterauf, Michael; Hannig, Frank; Teich, Jürgen (Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2024)

Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays - Walter, Dominik; Adamtschuk, Thomas; Hannig, Frank; Teich, Jürgen (Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2024)
LU decomposition is a widely used application for solving systems of linear equations. It involves decomposing a given matrix into a lower and upper triangular matrix. But if the matrix size is large, using a block-based LU decomposition on smaller submatrices can be advantageous. This approach allows for an adaptation to a target architecture’s memory and computing resources. In this paper, we analyze different strategies for mapping block LU decompositions onto Tightly Coupled Processor Arrays (TCPAs). Each decomposition introduces a dependence graph of matrix operations of smaller size: an unblocked LU decomposition, a triangular matrix solver, and a general matrix- matrix multiplication. First, we propose one piecewise regular algorithm for each corresponding loop nest, analyze its complexity, and then explore various reuse schemes for configuration, data, and synchronization. It will be shown that these schemes have a significant impact on the execution time of the entire algorithm and must be considered by the scheduling approach that governs the individual loop program invocations. Our performance analysis of the mapped block LU decomposition shows a maximal speedup of 12 on a TCPA of size 4 × 4 compared to a CPU, and a measured speedup of 10 measured on an FPGA-based SoC.<br

Co-Design of Sustainable Embedded Systems-on-Chip - Spieck, Jan; Walter, Dominik; Waschkeit, Jan; Teich, Jürgen (Design, Automation and Test in Europe Conference, 2025)

Co-Design of Systems-on-Chip for Sustainability - Spieck, Jan; Walter, Dominik; Waschkeit, Jan; Teich, Jürgen (NG-RES 2025: Sixth Workshop on Next Generation Real-Time Embedded Systems, 2025)

Europractice activity report 2024 - Walter, Dominik; Brand, Marcel; Heidorn, Christian; Witterauf, Michael; Hannig, Frank; Teich, Jürgen (2025)

Evaluation of CGRA Toolchains - Walter, Dominik; Halm, Marita; Seidel, Daniel; Ghosh, Indrayudh; Heidorn, Christian; Hannig, Frank; Teich, Jürgen (In Proceedings of the 1st Workshop on Open Source Solutions for Massively Parallel Integrated Circuits (OSSMPIC), 2025)
Increasing demands for computing power also propel the need for energy-efficient SoC accelerator architectures. One class for such accelerators are so-called processor arrays, which typically integrate a two-dimensional mesh of interconnected processing elements (PEs). Such arrays are specifically designed to accelerate the execution of multidimensional nested loops by exploiting the intrinsic parallelism of such loops. Coarse-grained reconfigurable arrays (CGRAs) belong to this class of accelerator architectures. In this work, we analyze four toolchains for mapping loop programs onto CGRAs and compare the resulting mappings wrt. performance, i.e., latency. While most toolchains succeed in simpler kernels like general matrix multiplication, some struggle to find valid mappings for more complex loops like a triangular solver. Furthermore, we observe that the considered CGRA mappers generally tend to underutilize the available PEs.

Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays - Heidorn, Christian; Walter, Dominik; Candir, Yunus Emre; Hannig, Frank; Teich, Jürgen (Proceedings of the 31st International Conference on Field Programmable Logic and Applications (FPL), 2021)
The advent of deep learning has revolutionized the domain of computer vision. Convolutional neural networks (CNNs) became state-of-the-art for solving complex tasks thanks to technological advances of high-end accelerators, such as GPUs and FPGAs, combined in clusters or cloud solutions. In embedded systems, CNNs are also of great interest. However, often these devices cannot afford to offload computational-intensive workloads to the cloud due to strict energy or real-time constraints. Tightly Coupled Processor Arrays (TCPAs) are ideal architectures for accelerating nested loop programs at high energy efficiency. In this demonstrator, we show how TCPAs can meet these requirements at the edge of computing. For illustration, we designed a CNN-based hand sign recognition which is accelerated on a TCPA, implemented the TCPA prototypically as an overlay on a Xilinx Zynq System-on-a-Chip (SoC), and showcase tremendous speedups compared with the integrated ARM Cortex-A9 processor.
Keywords: Convolutional Neural Networks; Hardware Acceleration; Coarse-Grained Reconfigurable Array

Invasive Computing - Anantharajaiah, Nidhi; Asfour, Tamim; Bader, Michael; Bauer, Lars; Becker, Jürgen; Bischof, Simon; Brand, Marcel; Bungartz, Hans-Joachim; Eichler, Christian; Esper, Khalil; Falk, Joachim; Fasfous, Nael; et al. (FAU University Press, 2022)

Invasive Tightly-Coupled Processor Arrays - Teich, Jürgen; Brand, Marcel; Hannig, Frank; Heidorn, Christian; Walter, Dominik; Witterauf, Michael (Invasive Computing, 2022)

LION: Real-Time I/O Transfer Control for Massively Parallel Processor Arrays - Walter, Dominik; Teich, Jürgen (Proceedings of the 19th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), 2021)
The performance of many accelerator architectures depends on the communication with external memory. During execution, new I/O data is continuously fetched forth and back to memory. This data exchange is very often performance-critical and a careful orchestration thus vital. To satisfy the I/O demand for accelerators of loop nests, it was shown that the individual reads and writes can be merged into larger blocks, which are subsequently transferred by a single DMA transfer. Furthermore, the order in which such DMA transfers must be issued, was shown to be reducible to a real-time task scheduling problem to be solved at run time. Rather than just concepts, we investigate in this paper the architecture and implementation of such a Loop I/O Controller (LION) for a class of CGRAs called TCPAs. Based on a novel heap-based priority queue approach, the proposed controller is able to issue every 6 cycles a new DMA request to a memory bus. Even on a simple FPGA prototype running at just 200 MHz, this allows for more than 33 million DMA requests to be issued per second. Since the execution time of a typical DMA request is in general at least one order of magnitude longer, we can conclude that this rate is sufficient to fully utilize a memory bus. In the evaluation of our architecture, we compare the proposed priority queue with various state-of-the-art approaches and conclude that our priority queue is not only cheaper, but also guaranteeing real-time constraints. Furthermore, we discuss many different optimizations for the Loop I/O Controller, which can reduce the area of the proposed architecture significantly. <br

Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays - Walter, Dominik; Witterauf, Michael; Teich, Jürgen (Proceedings of the 18th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), 2020)
A fundamental problem of massively parallel ac- celerator architectures is the management of typically small peripheral I/O buffers that decouple the accelerator from an external memory. Very often, these buffers cannot store the entire input and output data of one execution and must be updated, i.e., filled or drained, frequently. Moreover, if a processor array performs either a read on an empty bank or a write on a full bank, it must interrupt its execution immediately until the corresponding data transfer between the accelerator and an external memory has been carried out. As a consequence, the timing predictability of the array execution might be impaired. Therefore, a precise analysis of a schedule for all data transfers is inevitable. But the sequence of all data transfers cannot be stored entirely inside most accelerators. Thus, we must determine and schedule all necessary data transfers dynamically at runtime. In this paper, we present an approach to characterize all necessary data transfers and to issue them in advance so that the peripheral I/O buffers never run full or empty. Here, it is shown first that a deadline for each data transfer can be derived from a given loop schedule resulting in a traditional task scheduling program. Unfortunately, however, standard real-time scheduling techniques such as earliest deadline first (EDF) cannot be applied here, as each data transfer must not be interrupted and even existing non-preemptive variants of EDF are known to be prone to timing anomalies. As a solution, we present a strictly non-work-conserving variant of EDF together with an efficient schedulability test for periodic loop executions. In an experimental section, the scheduling approach is applied to a randomly generated set of loop programs observing that our algorithm is able to feasibly schedule 95% of the theoretically schedulable problem instances. Altogether, we provide a fully timing-predictable buffer management for massively parallel processor arrays that avoids any I/O related stalls of a processor array by construction.<br
Keywords: TCPA; Puffer; I/O Schedule

Symbolic Loop Compilation for Tightly Coupled Processor Arrays - Witterauf, Michael; Walter, Dominik; Hannig, Frank; Teich, Jürgen (ACM Transactions on Embedded Computing Systems, 2021)
Tightly Coupled Processor Arrays (TCPAs), a class of massively parallel loop accelerators, allow applications to offload computationally expensive loops for improved performance and energy efficiency. To achieve these two goals, executing a loop on a TCPA requires an efficient generation of specific programs as well as other configuration data for each distinct combination of loop bounds and number of available processing elements (PEs). Since both these parameters are generally unknown at compile time—the number of available PEs due to dynamic resource management, and the loop bounds because they depend on the problem size—, both the programs and configuration data must be generated at runtime. However, pure just-in-time compilation is impractical because mapping a loop program onto a TCPA entails solving multiple NP-complete problems. As a solution, this article proposes a a unique mixed static/dynamic approach called symbolic loop compilation. It is shown that at compile time, the NP-complete problems (modulo scheduling, register allocation, and routing) can still be solved to optimality in a symbolic way resulting in a so-called symbolic configuration, a space-efficient intermediate representation parameterized in the loop bounds and number of PEs. This phase is called symbolic mapping. At runtime, for each requested accelerated execution of a loop program with given loop bounds and known number of available PEs, a concrete configuration, including PE programs and configuration data for all other components, is generated from the symbolic configuration according to these parameter values. This phase is called instantiation. We describe both phases in detail and show that instantiation runs in polynomial time with its most complex step, program instantiation, not directly depending on the number of PEs and thus scaling to arbitrary sizes of TCPAs. To validate the efficiency of this mixed static/dynamic compilation approach, we apply symbolic loop compilation to a set of real-world loop programs from several domains, measuring both compilation time and space requirements. Our experiments confirm that a symbolic configuration is a space-efficient representation suited for systems with little memory—in many cases, a symbolic configuration is smaller than even a single concrete configuration instantiated from it—and that the times for the run-time phase of program instantiation and configuration loading are negligible and moreover independent of the size of the available processor array. To give an example, instantiating a configuration for a matrix-matrix multiplication benchmark takes equally long for 4x4 and 32x32 PEs.