A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification - Reiser, Daniel; Reichel, Peter; Pechmann, Stefan; Mallah, Maen; Oppelt, Maximilian P.; Hagelauer, Amelie; Breiling, Marco; Fey, Dietmar; Reichenbach, Marc (Journal of Low Power Electronics and Applications, 2022)
In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design that is generic enough in the design process to be used for different applications, but specific in the hardware implementation to waste no energy for a given application. Therefore, we present a novel framework that allows an end-to-end ASIC implementation of a low-power hardware for time series classification using NNs. This includes a neural architecture search (NAS), which optimizes the NN configuration for accuracy and energy efficiency at the same time. This optimization targets a custom designed hardware architecture that is derived from the key properties of time series classification tasks. Additionally, a hardware generation tool is used that creates a complete system from the definition of the NN. This system uses local multi-level RRAM memory as weight and bias storage to avoid external memory access. Exploiting the non-volatility of these devices, such a system can use a power-down mode to save significant energy during the data acquisition process. Detection of atrial fibrillation (AFib) in electrocardiogram (ECG) data is used as an example for evaluation of the framework. It is shown that a reduction of more than 95% of the energy consumption compared to state-of-the-art solutions is achieved.
CRIS-Team WoS Importer:2022-04-08

A low-power rram memory block for embedded, multi-level weight and bias storage in artificial neural networks - Pechmann, Stefan; Mai, Timo; Potschka, Julian; Reiser, Daniel; Reichel, Peter; Breiling, Marco; Reichenbach, Marc; Hagelauer, Amelie (Micromachines, 2021)
Pattern recognition as a computing task is very well suited for machine learning algorithms utilizing artificial neural networks (ANNs). Computing systems using ANNs usually require some sort of data storage to store the weights and bias values for the processing elements of the individual neurons. This paper introduces a memory block using resistive memory cells (RRAM) to realize this weight and bias storage in an embedded and distributed way while also offering programming and multi-level ability. By implementing power gating, overall power consumption is decreased significantly without data loss by taking advantage of the non-volatility of the RRAM technology. Due to the versatility of the peripheral circuitry, the presented memory concept can be adapted to different applications and RRAM technologies.
CRIS-Team Scopus Importer:2021-11-05
Keywords: ANN; Embedded memory; Low-power; Memory block; Multi-level; RRAM

A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories - Knödtel, Johannes; Fritscher, Markus; Reiser, Daniel; Fey, Dietmar; Breiling, Marco; Reichenbach, Marc (9th International Conference on Modern Circuits and Systems Technologies, MOCAST 2020, Bremen, Germany, September 7-9, 2020, 2020)
With the emergence of DNN accelerators the main focus of such systems usually lies on utilizing local memories and reducing the size of the processed data, since delay and energy consumption are dominated by data transfer. Utilizig emerging memory technologies, such as ReRAMs, these goals might be attained much easier, due to advantageous non-functional and functional properties.One of the key drawbacks of such systems are reliability and variability of devices of such technologies. To certain degree, DNNs are resilient to soft and hard errors in their memory cells, so these issues might be surmountable depending on the device properties, but eludes trivial analyses known from the digital domain. Here the dynamic behavior of the devices comes into play and must be simulated in order to get a decent degree of confidence on the reliability of the hardware and therefore also yield.In order to tackle this issue we present an accelerator architecture and matching analysis pipeline that allows the user to specify and train a net topology and then test the design against some input activations with different randomized device properties. Using this approach we can estimate the inference results and other system and algorithm level properties in presence of different device level properties which might for example be extracted from real world measurements. Such a system can help the user in the design of their net or give them hints on the required device properties for a given net or aid them in evaluating existing designs.
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Fast HBM Access with FPGAs: Analysis, Architectures, and Applications - Holzinger, Philipp; Reiser, Daniel; Hahn, Tobias; Reichenbach, Marc (IEEE International Parallel and Distributed Processing Symposium Workshops, 2021)

Simulating large neural networks embedding MLC RRAM as weight storage considering device variations - Fritscher, Markus; Knödtel, Johannes; Reiser, Daniel; Mallah, Maen; Pechmann, Stefan; Fey, Dietmar; Reichenbach, Marc (Proc. of 12th IEEE Latin America Symposium on Circuits and System, 2021)