Aarith: An Arbitrary Precision Number Library - Keszöcze, Oliver; Brand, Marcel; Witterauf, Michael; Heidorn, Christian; Teich, Jürgen (ACM/SIGAPP Symposium On Applied Computing, 2021)

A fast BDD Minimization Framework for Approximate Computing - Wendler, Andreas; Keszöcze, Oliver (Design, Automation and Test in Europe, 2020)
Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as reduced area, increased computation speed, or power reduction. Computing the error of the approximated design is an essential step to determine its quality. The computation time for determining the error can become very large, effectively rendering the entire logic approximation procedure infeasible. As a remedy, we present methods to accelerate the computation of error metric computations by (a) exploiting structural information and (b) computing estimates of the metrics for multi-output Boolean functions represented as BDDs. We further present a novel greedy, bucket-based BDD minimization framework employing the newly proposed error metric computations to produce Pareto-optimal solutions with respect to BDD size and multiple error metrics. The applicability of the proposed minimization framework is demonstrated by an experimental evaluation. We can report considerable speedups while, at the same time, creating high-quality approximated BDDs.
Keywords: Approximate Computing; Design Space Exploration; Multi-Objective Optimization; BDD Minimization; Logic Minimization

A General and Exact Routing Methodology for Digital Microfluidic Biochips - Keszocze, Oliver; Wille, Robert; Chakrabarty, Krishnendu; Drechsler, Rolf (34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, 2016)

A Human-Centered Approach to Routing for Digital Microfluidic Biochips - Keszocze, Oliver; Pols, Andre; Drechsler, Rolf (Workshop on Design Automation for Understanding Hardware Designs, 2017)

A Logic for Cardinality Constraints - Riener, Heinz; Keszocze, Oliver; Drechsler, Rolf; Fey, Görschwyn (Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014)

An active set approach to the elastic-net and its applications in mass spectrometry - Alexandrov, Theodore; Keszocze, Oliver; Lorenz, Dirk; Schiffler, Stefan; Steinhorst, Klaus (Signal Processing with Adaptive Sparse Structured Representations, 2009)

An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs - Wille, Robert; Keszocze, Oliver; Othmer, Lars; Thomsen, Michael Kirkedal; Drechsler, Rolf (Journal of Low Power Electronics, 2017)
Keywords: Reversible Circuits; Synthesis; Hardware Descriptions Languages; Hoare Logic; Control Flow

Approximate Computing - Keszöcze, Oliver (it - Information Technology, 2022)
CRIS-Team WoS Importer:2022-05-20

Approximate Computing Extensions for the Clash HDL Compiler - Keszöcze, Oliver; Kießling, Michael (Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2021)
Approximate Computing is a novel design paradigm sacrificing computational accuracy for gains in other non-functional properties, such as area, latency, and power consumption. Many approximation techniques operate on the netlist of a circuit. We believe that working on a higher level of abstraction is beneficial. For this, we chose the high-level hardware description language Clash. The language is based on the functional programming language Haskell, i.e. describes hardware in a very abstract manner allowing to focus on the functionality instead of technical details. We extend the Clash compiler to support multiple approximation techniques. Initial experiments show promising results with respect to reductions in area, latency, and power consumption of the synthesized approximated circuits.<br

Artificial Intelligence for Molecular Communication - Bartunik, Max; Kirchner, Jens; Keszöcze, Oliver (it - Information Technology, 2023)
Keywords: Molecular Communication; Demodulation; Convolutional Neural Network

BDD-based Error Metric Analysis, Computation and Optimization - Keszöcze, Oliver (IEEE Access, 2022)
Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as reduced area, increased computation speed, or power reduction. Computing the error of the approximated design is an essential step to determine its quality. The computation time for determining the error can become very large, effectively rendering the entire logic approximation procedure infeasible. In this work we extensively analyze various error metrics and approximation operations.We present methods to accelerate the computation of error metric computations by (a) exploiting structural information of the function obtained by applying the analyzed operations and (b) computing estimates of the metrics for multi-output Boolean functions represented as Binary Decision Diagrams (BDDs). We further present a novel greedy, bucket-based BDD minimization framework employing the newly proposed error metric computations to produce Pareto-optimal solutions with respect to BDD size and multiple error metrics. The applicability of the proposed minimization framework is demonstrated by an experimental evaluation. We can report considerable speedups while, at the same time, creating high-quality approximated BDDs. The presented framework is publicly available as open-source software on GitHu
CRIS-Team Scopus Importer:2022-01-21
Keywords: Approximate Computing; BDD Minimization; Design Space Exploration; Error Metrics; Logic Minimization; Multi-Objective Optimization

BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips - Stoppe, Jannis; Keszocze, Oliver; Luenert, Maximilian; Wille, Robert; Drechsler, Rolf (2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, 2017)
Keywords: Java; libgdx; Grammar; Interactive; Synthesis; Visualization; DMFBs; Biochips

Chatbot-Based Assertion Generation from Natural Language Specifications - Keszöcze, Oliver; Harris, Ian G. (Forum on Specification & Design Languages (FDL), 2019)
We present an approach to simplify the task of ex tracting assertions from specifications given in natural language. Our goal is to accept and understand a broad range of linguistic variation, allowing the author of the natural language specifications to express herself freely. To enable this, we leverage the Dialogflow framework from Google. Dialogflow is usually used to build chatbots that understand and respond to conversational statements. We have trained a Dialogflow model to recognize a range of different natural language expressions of properties, and to identify key information inside the expression. The model responses to each statement with a generated SystemVerilog assertion whose semantic meaning is equivalent to that of the English statement.<br
Keywords: Assertion-based Verification; Natural Language Understanding; Automatic Assertion Generation; Assertion Mining

Compiler-based Processor Network Generation for Neural Networks on FPGAs - Plagwitz, Patrick; Hannig, Frank; Teich, Jürgen; Keszöcze, Oliver (Proceedings of the 27th Workshop on Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV), 2024)
The fast-moving field of Neural Network (NN) research has brought breakthroughs in application domains like image or natural language processing. However, since new techniques are constantly emerging, fast prototyping of Neural Networks on edge devices like Field-Programmable Gate Arrays (FPGAs) is particularly appealing due to their reconfigurability. Existing compiler-based toolchains generating specialized hardware are rare and restricted in their scope and coverage. In this paper, we propose a novel NN model-to-hardware flow that exploits the capabilities of Application-Specific Instruction Set Processors (ASIPs) and networks that can be built to implement NNs in a scalable and mixed hardware/software-reconfigurable way. Starting with an NN specification in PyTorch, an ASIP network generation toolchain is presented in which each instantiated core is assigned a portion of neurons to execute a given NN in a parallel and pipelined way while tailoring the instruction set of each core to the computations of the neurons. In addition, we propose multiple ML-specific instruction set extensions realized in hardware, including bit width-restricted ALU operations and activation functions with the circuits automatically generated from a given C/C++ implementation. Experimental results include a design space exploration of alternative implementations for the design objectives of FPGA resource usage, latency, and throughput. Our approach is shown to achieve higher speed-ups than similar processor-based approaches while consuming lower amounts of resources.<br

Computational Complexity of Error Metrics in Approximate Computing - Keszöcze, Oliver; Soeken, Mathias; Drechsler, Rolf (Further Improvements in the Boolean Domain, 2018)
The amount of digital systems supporting our daily life is increasing continuously. Improved technical facilities for their production have led to growing challenges for engineers and scientists working in the Boolean domain. A Boolean variable can only carry two different Boolean values: FALSE or TRUE (0 or 1), and has the best interference resistance in technical systems. However, a Boolean function exponentially depends on the number of its variables. This exponential complexity is the reason for major problems in the process of design and realization of circuits. According to Moore’s Law, the complexity of digital systems approximately doubles every 18 months. This requires comprehensive knowledge and techniques to solve very complex Boolean problems. This volume represents the third book in a series that provides further insights into the Boolean domain. Part 1 explores powerful models, methods and techniques which improve the efficiency in solving Boolean problems of extreme complexity. The universality of Boolean equations as a model to solve Non-deterministic Polynomial-time (NP) hard problems, as well as special properties of index generation functions, spectral techniques, or relational approaches, is discussed here. Both hardware devices, such as Field Programmable Gate Arrays (FPGAs) or Graphics Processing Units (GPUs), and optimized algorithms realized in software contribute to the acceleration of Boolean calculations. Part 2 contributes to the synthesis and visualization of digital circuits, and provides interesting new solutions for several types of circuits. A comprehensive collection of benchmarks supports the evolution of both existing and new synthesis approaches. The continuous reduction of the size of the transistors increases the challenges with regard to the reliability of the circuits. Part 3 describes several new approaches for the synthesis of reversible circuits. These approaches, as well as a classification of reversible functions, extend the basis of future quantum computer

ConfidenceSat: A Parallel SAT Solver with Conflict Clause Handling - Schmitz, Kenneth; Keszocze, Oliver; Tietjen, Jil; Drechsler, Rolf (International Workshop on Boolean Problems, 2018)

Deep Learning to Demodulate Transmissions in Molecular Communication - Bartunik, Max; Keszöcze, Oliver; Schiller, Benjamin; Kirchner, Jens (Proceedings of the 6th Workshop on Molecular Communications, 2022)

Der Einfluss von Zellformen Auf Das Routing von Digital Microfluidic Biochips - Schneider, Leonard; Keszocze, Oliver; Stoppe, Jannis; Drechsler, Rolf (Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017)

Design and Error Analysis of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Keszöcze, Oliver; Khosravi, Faramarz; Becher, Andreas; Teich, Jürgen (it - Information Technology, 2022)
We present the design and a closed-form error analysis of accuracy-configurable multipliers via segmented carry chains. To address this problem, we model the approximate partial-product accumulations as a sequential process. According to a given splitting point of the carry chains, the technique herein discussed allows varying the quality of the accumulations and, consequently, the overall product. Due to these shorter critical paths, such kinds of approximate multipliers can trade-off accuracy for an increased performance whilst exploiting the inherent area savings of sequential over combinatorial approaches. We implemented multiple architectures targeting FPGAs and ASICs with different bit-widths and accuracy configurations to 1) estimate resources, power consumption, and delay, as well as to 2) evaluate those error metrics that belong to the so-called #P-complete class.<br
Keywords: Approximate computing; Sequential Multiplier; Error Analysis

Design Space Exploration of Time, Energy, and Error Rate Trade-oﬀs for CNNs using Accuracy-Programmable Instruction Set Processors - Schuster, Armin; Heidorn, Christian; Brand, Marcel; Keszöcze, Oliver; Teich, Jürgen (Joint European Conference on Machine Learning and Principles and Practice of Knowledge Discovery in Databases (ECML PKDD 2021), 2021)
We proclaim the use of application-speciﬁc instruction set processors with programmable accuracy called Anytime Instruction Processors (AIPs) for Convolutional Neural Network (CNN) inference. For a ﬂoating-point operation, the number of correctly computed mantissa result bits can be freely adjusted, allowing for a ﬁne-grained trade-oﬀ analysis between accuracy, execution time and energy. We propose a Design Space Exploration (DSE) technique in which the accuracy of CNN computations is determined layer-by-layer. As one result, we show that reductions of up to 62% in energy consumption are achievable for a representative ResNet-18 benchmark in comparison to a solution where each layer is computed at full accuracy according to the IEEE 754 single precision ﬂoating-point format.<br

DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks - Sommer, Jan; Özkan, Mehmet Akif; Keszöcze, Oliver; Teich, Jürgen (IEEE Proceedings of the 32nd International Conference on Field Programmable Logic and Applications, 2022)
The number of Digital Signal Processor (DSP) resources available in Field Programmable Gate Arrays (FPGAs) is often quite limited. Therefore, full utilization of available DSP resources for the computationally intensive parts of an algorithm is paramount for optimizing the non-functional properties of an implementation (i.e., performance, power, and area). The DSPs available in Xilinx devices implement large bit width operators (i.e. a 48-bit accumulator or a 18 x 27 multiplier). However, using such a DSP for low-precision quantized data (as is common in image processing or machine learning applications) leaves the DSP resources underutilized. As a remedy, a method has been proposed to pack and compute four 4-bit multiplications on a single DSP in a single clock cycle. This paper presents a generalization of this scheme to arbitrary bit widths and number of multiplications. We also demonstrate that the previously proposed approach leads to errors (Mean Absolute Error (MAE) = 0.37). Furthermore, we explain where these errors come from and how they can be corrected. On top, we introduce a novel approximate method called "Overpacking" which allows to squeeze even more multiplications into a single DSP at the cost of small errors (MAE = 0.47). Overpacking allows to squeeze six 4-bit multiplications into a single DSP compared to just four in the literature. Finally, we introduce an alternative method for packing multiple small-bit width additions into a single 48-bit accumulator for use in applications such as Spiking Neural Networks. <br
Keywords: dsp; fpga; approximation; approximate computing

Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips - Schneider, Leonard; Keszocze, Oliver; Stoppe, Jannis; Drechsler, Rolf (20th Design, Automation and Test in Europe, DATE 2017, 2017)

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks - Sommer, Jan; Özkan, Mehmet Akif; Keszöcze, Oliver; Teich, Jürgen (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022)
Spiking neural networks (SNNs) compute in an event-based manner to achieve a more efficient computation than standard neural networks. In SNNs, neuronal outputs are not encoded as real-valued activations but as sequences of binary spikes. The motivation of using SNNs over conventional neural networks is rooted in the special computational aspects of spike-based processing, especially the high degree of sparsity of spikes. Well-established implementations of convolutional neural networks (CNNs) feature large spatial arrays of processing elements (PEs) that remain highly underutilized in the face of activation sparsity. We propose a novel architecture optimized for the processing of convolutional SNNs (CSNNs) featuring a high degree of sparsity. The proposed architecture consists of an array of PEs of the size of the kernel of a convolution and an intelligent spike queue that provides a high PE utilization. A constant flow of spikes is ensured by compressing the feature maps into queues that can then be processed spike-by-spike. This compression is performed at run-time, leading to a self-timed schedule. This allows the processing time to scale with the number of spikes. Also, a novel memory organization scheme is introduced to efficiently store and retrieve the membrane potentials of the individual neurons using multiple small parallel on-chip RAMs. Each RAM is hardwired to its PE, reducing switching circuitry. We implemented the proposed architecture on an FPGA and achieved a significant speedup compared to previously proposed SNN implementations ( 10 times) while needing less hardware resources and maintaining a higher energy efficiency ( 15 times
Keywords: Event-based processing; field-programmable gate array (FPGA); hardware acceleration; spiking convolutional neural networks (SNNs)

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks - Sommer, Jan; Özkan, Mehmet Akif; Keszöcze, Oliver; Teich, Jürgen (International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2022)
Spiking neural networks (SNNs) compute in an event-based manner to achieve a more efficient computation than standard neural networks. In SNNs, neuronal outputs are not encoded as real-valued activations but as sequences of binary spikes. The motivation of using SNNs over conventional neural networks is rooted in the special computational aspects of spike-based processing, especially the high degree of sparsity of spikes. Well-established implementations of convolutional neural networks (CNNs) feature large spatial arrays of processing elements (PEs) that remain highly underutilized in the face of activation sparsity. We propose a novel architecture optimized for the processing of convolutional SNNs (CSNNs) featuring a high degree of sparsity. The proposed architecture consists of an array of PEs of the size of the kernel of a convolution and an intelligent spike queue that provides a high PE utilization. A constant flow of spikes is ensured by compressing the feature maps into queues that can then be processed spike-by-spike. This compression is performed at run-time, leading to a self-timed schedule. This allows the processing time to scale with the number of spikes. Also, a novel memory organization scheme is introduced to efficiently store and retrieve the membrane potentials of the individual neurons using multiple small parallel on-chip RAMs. Each RAM is hardwired to its PE, reducing switching circuitry. We implemented the proposed architecture on an FPGA and achieved a significant speedup compared to previously proposed SNN implementations ( 10 times) while needing less hardware resources and maintaining a higher energy efficiency ( 15 times
Keywords: Event-based processing; field-programmable gate array (FPGA); hardware acceleration; spiking convolutional neural networks (SNNs)

Efficient One-Pass Synthesis for Digital Microfluidic Biochips - Mohammadzadeh, Naser; Wille, Robert; Keszöcze, Oliver (ACM Transactions on Design Automation of Electronic Systems, 2021)

Error Analysis for Loop Programs using Anytime Instructions in Approximate Computing - Keszöcze, Oliver; König, Moritz; Brand, Marcel; Teich, Jürgen (Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2020)
Approximate Computing is a novel design paradigm sacrificing computational accuracy for gains in other non-functional properties. We present a tool that allows to automatically analyze approximated loop programs for the resulting error and range of output values. Our tool allows to model non-uniform distributions for the input variables. We further support the novel concept of Anytime Instructions: Anytime Instructions encode the number of most-significant mantissa bits to be computed in floating point operations. They are typically used to achieve execution time and energy reductions. First experiments using the tool show promising results.<br

Exact Design of Digital Microfluidic Biochips - Keszöcze, Oliver; Wille, Robert; Drechsler, Rolf (Springer, 2018)

Exact One-Pass Synthesis of Digital Microfluidic Biochips - Keszocze, Oliver; Wille, Robert; Ho, Tsung-Yi; Drechsler, Rolf (51st Annual Design Automation Conference, DAC 2014, 2014)

Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures - Keszöcze, Oliver; Mohammadzadeh, Naser; Wille, Robert (Design, Automation and Test in Europe, 2021)

Exact Routing for Digital Microfluidic Biochips with Temporary Blockages - Keszocze, Oliver; Wille, Robert; Drechsler, Rolf (2014 33rd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, 2015)

Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips - Keszocze, Oliver; Li, Zipeng; Grimmer, Andreas; Wille, Robert; Chakrabarty, Krishnendu; Drechsler, Rolf (22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, 2017)

Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips - Keszocze, Oliver; Ibrahim, Mohamed; Wille, Robert; Chakrabarty, Krishnendu; Drechsler, Rolf (31st International Conference on VLSI Design, VLSID 2018, 2018)
Keywords: Microfluidics; Resource allocation; Dmfb; Biomolecular protocols

Exakter Entwurf digitaler mikrofluidischer Biochips - Keszocze, Oliver (Ausgezeichnete Informatikdissertationen 2017, 2018)
Keywords: Enwturf; Biochips

Execution Environment for Dynamic Software Runtime Examination - Schmitz, Kenneth; Keszocze, Oliver; Stoppe, Jannis; Drechsler, Rolf (Workshop on Design Automation for Understanding Hardware Designs, 2018)

Exploiting Electronic Design Automation for Checking Legal Regulations: A Vision - Keszöcze, Oliver; Wille, Robert (Languages, Design Methods, and Tools for Electronic System Design, 2016)
This book brings together a selection of the best papers from the seventeenth edition of the Forum on specification and Design Languages Conference (FDL), which took place on October 14-16, 2014, in Munich, Germany. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology system

Extensive resilience analysis of function models of complex systems - Guillouët, Yann; Keszöcze, Oliver; Sill Torres, Frank (Resilience Week, 2021)
The knowledge about the responses to hazardous events is of importance throughout the whole life cycle of a complex system, regardless whether during design or operation phases. These responses also allow to draw conclusions about the resilience of the system. Consequently, there is a need for an extensive consideration of all possible hazardous events a system can be exposed to. This work presents a method for determining the hazards with the most critical system response in terms of resilience. Therefore, we introduce a method for modeling failure propagation under consideration of dynamic behavior in function models. This method is then extended for assessing resilience for random hazard scenarios. Finally, we propose two solutions for determining the most critical hazard scenarios, and thus, provide a base for improvements of the system.<br
Keywords: resilience; hazards; function models; complex systems; evolutionary algorithm

Fast Approximate AIG-Based Synthesis - Heil, Annika; Keszöcze, Oliver (International Workshop on Boolean Problems, 2022)
Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as smaller area, shorter delay, or less power consumption. Synthesizing approximate circuits is a difficult task due to the inherent complexity of evaluating error metrics used to indicate the quality of the approximated circuit. We present a novel and fast greedy, bucket-based Approximate Logic Synthesis technique working on AND-Inverter Graphs that iteratively performs XOR and constant replacements. It minimizes both, the area of the approximated circuit and, the error introduced by the approximations. We exploit properties of the replacement operations to speed up the computation of the weighted Hamming distance error metric, allowing the algorithm to have a very short execution time. The effectiveness of the presented method is evaluated in a set of experiments, including the state-of-the-art benchmark library EvoApproxLibLITE<br
Keywords: Approximate Computing; (XOR)-And-Inverter Graph; Logic Synthesis

Fast Approximate AIG-Based Synthesis - Heil, Annika; Keszöcze, Oliver (Advanced Boolean Techniques, 2023)
Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as smaller area, shorter delay, or less power consumption. Synthesizing approximate circuits is a difficult task due to the inherent complexity of evaluating error metrics used to indicate the quality of the approximated circuit. We present a novel and fast greedy, bucket-based Approximate Logic Synthesis technique working on AND-Inverter Graphs that iteratively performs XOR and constant replacements. It minimizes both, the area of the approximated circuit and, the error introduced by the approximations. We exploit properties of the replacement operations to speed up the computation of the weighted Hamming distance error metric, allowing the algorithm to have a very short execution time. The effectiveness of the presented method is evaluated in a set of experiments, including the state-of-the-art benchmark library EvoApproxLibLITE</sup

Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits - Deb, Arighna; Wille, Robert; Keszocze, Oliver; Hillmich, Stefan; Drechsler, Rolf (ACM Journal on Emerging Technologies in Computing Systems, 2016)
Optical circuits are considered a promising emerging technology for applications in ultra-high-speed networks or interconnects. However, the development of (automatic) synthesis approaches for such circuits is still in its infancy. Although first generic and automatic synthesis approaches have been proposed, no clear understanding exists yet on how to keep the costs of the resulting circuits as small as possible. In the domain of optical circuits, this is particularly interesting for the number of gates and the effect of so-called splitters to the signal strength. In this work, we investigate this relation by considering a variety of (existing as well as proposed) synthesis approaches for optical circuits. Our investigations show that reducing the number of gates and reducing the number of splitters are contradictory optimization objectives. Furthermore, the performance of synthesis guided with respect to gate efficiency as well as synthesis guided with respect to splitter freeness is evaluated and an overhead factor between the contradictory metrics is experimentally determined.
Keywords: Optical circuit; crossbar gate; splitter; worst-case fraction

Generating and Checking Control Logic in the HDL-Based Design of Reversible Circuits - Wille, Robert; Keszocze, Oliver; Othmer, Lars; Thomsen, Michael Kirkedal; Drechsler, Rolf (6th International Symposium on Embedded Computing and System Design, ISED 2016, 2017)

Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout - Lukac, Martin; Nursultan, Saadat; Krylov, Gerogiy; Keszöcze, Oliver (Euromicro Conference on Digital System Design, 2020)

Improving SAT Solving Using Monte Carlo Tree Search-Based Clause Learning - Keszocze, Oliver; Schmitz, Kenneth; Schloeter, Jens; Drechsler, Rolf (International Workshop on Boolean Problems, 2018)

Improving SAT Solving Using Monte Carlo Tree Search-based Clause Learning - Keszöcze, Oliver; Schmitz, Kenneth; Schloeter, Jens; Drechsler, Rolf (Advanced Boolean Techniques - Selected Papers from the 13th International Workshop on Boolean Problems, 2020)
Most modern state-of-the-art Boolean Satisfiability (SAT) solvers are based on the Davis-Putnam-Logemann-Loveland algorithm and exploit techniques like unit propagation and Conflict-Driven Clause Learning (CDCL). Even though this approach proved to be successful in practice, the success of the Monte Carlo Tree Search (MCTS) algorithm in other domains led to research in using it to solve SAT problems. A recent approach extended the attempt to solve SAT using a MCTS-based algorithm by adding CDCL. We further analyzed the behavior of that approach by using visualizations of the produced search trees and based on the analysis introduced multiple heuristics improving different aspects of the quality of the learned clauses. While the resulting solver can be used to solve SAT on its own, the real strength lies in the learned clauses. By using the MCTS solver as a preprocessor, the learned clauses can be used to improve the performance of existing SAT solvers.<br
Keywords: SAT; Satisfiability; SAT Solver; Monte Carlo Tree Search; Heuristic; SAT Preprocessing

Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Wille, Robert; Keszocze, Oliver; Othmer, Lars; Thomsen, Michael Kirkedal; Drechsler, Rolf (8th International Conference on Reversible Computation, RC 2016, 2016)

Lips: An IDE for Model Driven Engineering Based on Natural LanguagePprocessing - Keszocze, Oliver; Soeken, Mathias; Kuksa, Eugen; Drechsler, Rolf (2013 1st International Workshop on Natural Language Analysis in Software Engineering, NaturaLiSE 2013, 2013)

Look-Ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits - Wille, Robert; Keszocze, Oliver; Walter, Marcel; Rohrs, Patrick; Chattopadhyay, Anupam; Drechsler, Rolf (21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, 2016)

Markov Chain-based Optimization Time Analysis of Bivalent Ant Colony Optimization for Sorting and LeadingOnes - Kergaßner, Matthias; Keszöcze, Oliver; Wanka, Rolf (Genetic and Evolutionary Computation Conference (GECCO), 2024)
So far, only few bounds on the runtime behavior of Ant Colony Optimization (ACO) have been reported. To alleviate this situation, we investigate the ACO variant we call Bivalent ACO (BACO) that uses exactly two pheromone values. We provide and successfully apply a new Markov chain-based approach to calculate the expected optimization time, i. e., the expected number of iterations until the algorithm terminates. This approach allows to derive exact formulæ for the expected optimization time for the problems Sorting and LeadingOnes. It turns out that the ratio of the two pheromone values significantly governs the runtime be- havior of BACO. To the best of our knowledge, for the first time, we can present tight bounds for Sorting (Θ(n3)) with a specifically chosen objective function and prove the missing lower bound Ω(n2) for LeadingOnes which, thus, is tightly bounded by Θ(n2). We show that despite we have a drastically simplified ant algorithm with respect to the influence of the pheromones on the solving process, known bounds on the expected optimization time for the problems OneMax (O(n log n)) and LeadingOnes (O(n2)) can be re-produced as a by-product of our approach. Experiments validate our theoretical findings.<br
Keywords: Ant colony optimization; optimization time analysis; Markov chains

One-pass Synthesis for Digital Microfluidic Biochips: A Survey - Keszöcze, Oliver; Wille, Robert; Drechsler, Rolf (International Symposium on Devices, Circuits and Systems, 2020)
With the advances of the microfluidic technology, the design of Digital Microfluidic Biochips (DMFBs) received significant attention in the recent past. The corresponding design process usually consists of multiple, consecutive design tasks, namely binding, scheduling, placement, and routing. These tasks, however, are often considered and solved separately. This can lead to design gaps between the individual steps, yielding less-than-optimal overall solutions or prevent to solve the next step altogether. In order to address these shortcomings, the concept of one-pass synthesis for DMFBs has been introduced. In this survey paper, we review the main ideas of this concept and provide an overview on two different implementations of it: (1) an exact, SAT-based approach which guarantees optimal solutions with respect to area and/or timing and (2) a heuristic graph-based approach which focuses on run-time efficiency. We discuss the (dis-)advantages of those approaches with respect to their quality as well as scalability and illustrate them on various benchmark assays.<br
Keywords: DMFB; one-pass synthesis; survey; Biochips

On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Keszöcze, Oliver; Khosravi, Faramarz; Becher, Andreas; Teich, Jürgen (2021)

On the Complexity of Design Tasks for Digital Microfluidic Biochips - Keszocze, Oliver; Niemann, Philipp; Friedemann, Arved; Drechsler, Rolf (Microelectronics Journal, 2018)
Keywords: Pin assignment; Routing; Digital Microfluidic Biochips; Complexity

Peak Detection in Mass Spectrometry Data Using Sparse Coding - Alexandrov, Theodore; Steinhorst, Klaus; Keszocze, Oliver; Schiffler, Stefan (nternational Conference on Computational Statistics, 2010)

Precision- and Accuracy-Reconfigurable Processor Architectures—An Overview - Brand, Marcel; Keszöcze, Oliver; Teich, Jürgen (IEEE Transactions on Circuits and Systems II: Express Briefs, 2022)
High performance and, at the same time, energy efficiency are important yet often conflicting requirements in many fields of emerging applications. Those applications range from multi-dimensional and multi-sensor digital signal processing to machine learning, such as neural network processing. Whereas conventional fixed-point and floating-point processor architectures cannot adapt to quite diverging demands related to required precision and accuracy of computations, even within a single application, e.g., in different layers of a neural network, domain-specific accelerators may be much too specific and thus rigid to cover a wide enough spectrum of applications. In this tutorial brief, we give an overview of existing processor solutions that are reconfigurable or tunable in precision or accuracy of computations. The spectrum of reviewed architectures ranges from processors with vectorizable processors over multi- and trans-precision solutions, including GPUs to any-time instruction-set processors. The latter works with a fixed precision, but the accuracy of the result of floating-point operations is encoded in the instruction word. It can thus vary from instruction to instruction. This allows realizing accuracy vs. execution time or energy tradeoffs. Subsequently, we investigate several application domains, including neural network processing, linear algebra, and approximate computing, where such emerging processor architectures can be beneficially use
Keywords: Computer architecture; Arithmetic; Circuits and systems; Neural networks; Adders; Machine learning algorithms; Linear algebra; Accuracy; Reconfigurable architectures; Convolutional neural networks

Probabilistic Error Propagation through Approximated Boolean Networks - Echavarria Gutiérrez, Jorge Alfonso; Wildermann, Stefan; Keszöcze, Oliver; Teich, Jürgen (Proceedings of the 57th Annual Design Automation Conference, 2020)
Keywords: Approximate Computing; Error propagation

Probability-based DSE of Approximated LUT-based FPGA Designs - Echavarria Gutiérrez, Jorge Alfonso; Keszöcze, Oliver; Teich, Jürgen (15th IEEE Dallas Circuits and Systems Conference, 2022)

Refactoring of Quantum and Reversible Circuits - Lukac, Martin; Nursultan, Saadat; Krylov, Georgiy; Keszöcze, Oliver (International Workshop on Quantum Compilation, 2020)

Reverse BDD-Based Synthesis for Splitter-Free Optical Circuits - Wille, Robert; Keszocze, Oliver; Hopfmuller, Clemens; Drechsler, Rolf (2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, 2015)

Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems - Teich, Jürgen; Pourmohseni, Behnaz; Keszöcze, Oliver; Spieck, Jan; Wildermann, Stefan (Asia and South Pacific Design Automation Conference (ASP-DAC), 2020)
For many embedded applications, non-functional requirements such as safety, reliability, and execution time must be guaranteed in tight bounds on a given multi-core platform. Here, jitter in non-functional program execution qualities is caused either by outer influences such as faults injected by the environment, but can be induced also from the system management software itself, including thread-to-core mapping, scheduling and power management. A second huge source of variability typically stems from data-dependent workloads. In this paper, we classify and present techniques to enforce non-functional execution properties on multi-core programs. Based on a static design space exploration and analysis of influences of variability of non-functional properties, enforcement strategies are generated to guide the execution of periodically executed applications in given requirement corridors. Using the case study of a complex image streaming application, we show that by controlling DVFS settings of cores proactively, not only tight execution times, but also reliability requirements may be enforced dynamically while trying to minimize energy consumption.
Keywords: run-time enforcement; many-core systems; reliability; realtime

SAS - A Framework for Symmetry-based Approximate Synthesis - Jungnitz, Niklas; Keszöcze, Oliver (Design Automation Conference, 2024)
Approximate Computing is a design paradigm that trades off computational accuracy for gains in non-functional aspects such as reduced area, increased computation speed, or power reduction. The latter is of special interest in the field of Internet of Things. In this paper we present SAS, a framework for symmetry-based approximate logic synthesis. Given a Boolean multi-output function, SAS approximates it by (partially) replacing its output functions by symmetric functions with minimal Hamming distance. The framework is capable of restricting the introduced error with respect to a parameterized error metric that covers many real-word use-cases. Experimental results on common benchmark sets as well as large bit width arithmetic Boolean functions confirm the effectiveness of the proposed framework. SAS is capable of synthesizing Boolean functions with size reductions of up to ≈ 45% while, at the same time, respecting the specified threshold on the error metric. The framework is publicly available as open-source software on GitHub.<br
Keywords: Approximate Computing; BDD; AIG; Optimization; Logic Synthesis

Scalable One-Pass Synthesis for Digital Microfluidic Biochips - Wille, Robert; Keszocze, Oliver; Drechsler, Rolf; Boehnisch, Tobias; Kroker, Alexander (IEEE Design & Test, 2015)

(Semi-)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications - Keszocze, Oliver; Keiner, Bettina; Richter, Matthias; Antpöhler, Gottfried; Wille, Robert (Forum on Specification & Design Languages, 2014)

(Semi)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications - Keszöcze, Oliver; Keiner, Betina; Richter, Matthias; Antpöhler, Gottfried; Wille, Robert (Natural Language Processing for Electronic Design Automation, 2020)
Caused by the challenges in the design of today's hardware and software systems, tools for electronic design automation (EDA) became impressively powerful. However, these accomplishments can also be exploited in other domains. In fact, the steps of formalizing and checking legal regulations share many similarities with established EDA design steps. In this work, this is demonstrated by proposing the application of EDA tools in the domain of law processing. We propose a (semi)automatic translation of real rules and regulations into a formal representation. Afterwards, we discuss how-similar to the hardware/software design-these formalization can be utilized in the respective domain.
CRIS-Team Scopus Importer:2024-12-16
Keywords: Domain specific language; Electronic design automation; Formal representations; Legal regulations; Natural language processing; Object constraint language; Regular expressions; Text translation; Typed dependencies; Unified modeling language

SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation - Plagwitz, Patrick; Hannig, Frank; Teich, Jürgen; Keszöcze, Oliver (Proceedings of the 20th International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC), 2024)
Convolutional Neural Networks (CNNs) are widely employed to solve various problems, e.g., image classification. Due to their compute- and data-intensive nature, CNN accelerators have been developed as ASICs or on FPGAs. The increasing complexity of applications has caused resource costs and energy requirements of these accelerators to grow. Spiking Neural Networks (SNNs) are an emerging alternative to CNN implementations, promising higher resource and energy efficiency. The main research question addressed in this paper is whether SNN accelerators truly meet these expectations of reduced energy demands compared to their CNN equivalents when implemented on modern FPGAs. For this purpose, we analyze multiple SNN hardware accelerators for FPGAs regarding performance and energy efficiency. We also present a novel encoding scheme of spike event queues and a novel memory organization technique to improve SNN energy efficiency further. Both techniques have been integrated into a state-of-the-art SNN architecture and evaluated for MNIST, SVHN, and CIFAR-10 data sets and corresponding network architectures on two differently sized modern FPGA platforms. A result of our empirical analysis is that for complex benchmarks such as SVHN and CIFAR-10, SNNs do live up to their expectations.<br

Synthese- und Optimierungsverfahren für zukünftige Computerparadigmen - Wille, Robert; Keszocze, Oliver; Drechsler, Rolf (Shaker, 2015)
Die Entwicklung von Computertechnologien befindet sich vor einer Zeitenwende. Physikalische Grenzen bisheriger Technologien werden früher oder später erreicht werden, was eine Weiterentwicklung von Rechensystemen auf Basis konventioneller Paradigmen immer schwieriger macht. Bereits heute lassen sich vereinzelt Anzeichen dafür finden: Die Performanz heutiger Rechner wird oft nicht mehr nur durch tatsächliche Leistungssteigerung der Prozessoren erreicht, sondern z.B. durch einfache Duplizierung mittels Mehrkernprozessoren. Als Konsequenz dieser Entwicklung beschäftigen sich Wissenschaftler und Ingenieure bereits seit vielen Jahren mit der Entwicklung alternativer Computertechnologien. Während es sich hierbei in vielen Fällen noch um Grundlagenforschung handelt, existieren aber bereits auch erste Prototypen - mit vielversprechenden Ergebnissen. Zu den neuen Formen von Computertechnologien zählen dabei unter anderem Quantencomputer, Reversible Computer, Optische Computer oder Biochips. Neben den vielversprechenden Anwendungsmöglichkeiten dieser neuen Technologien ergeben sich aber neue Fragestellungen. So müssen wie bei heutigen Technologien entsprechende Schaltungen effizient entworfen werden. Konventionelle Methoden lassen sich hierfür aber nicht unbedingt direkt für die neuen Computerparadigmen umsetzen. Daher müssen Verfahren zum Entwurf solcher Schaltungen neu entwickelt werden. Dieser Aufgabe hat sich eine Gruppe von acht Studierenden der Informatik an der Universität Bremen im einjährigen studentischen Projekt CompTech gewidmet. Ziel des Projektes war die Entwicklung und Verbesserung von Entwurfsverfahren für zukünftige Computertechnologien. Das vorliegende Buch ist eine Zusammenfassung der im Rahmen des Projektes erzielten Ergebnisse
Keywords: Hardwareentwurf; optische Schaltkreise; Quantum Computing; Reversible Computing; Biochips

Synthesis of Approximate Coders for On-Chip Interconnects Using Reversible Logic - Wille, Robert; Keszocze, Oliver; Hillmich, Stefan; Walter, Marcel; Garcia-Ortiz, Alberto (19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, 2016)

Synthesis of Optical Circuits Using Binary Decision Diagrams - Deb, Arighna; Wille, Robert; Keszocze, Oliver; Shirinzadeh, Saeideh; Drechsler, Rolf (Integration-The Vlsi Journal, 2017)
The advances in silicon photonics motivated the consideration of optical circuits as a new and emerging circuit technology. In particular for ultra-fast interconnects, optical circuits may provide a suitable alternative since it avoids the conversion of signals from the optical to the electrical domain. Accordingly, design automation of this kind of circuits received significant attention. In this work, we consider synthesis of optical circuits based on Binary Decision Diagrams (BDDs). Although BDDs allow for a direct mapping of the function representation to an optical circuit (and, hence, a scalable synthesis), they have their shortcomings with respect to dedicated cost metrics. In this work, we investigate this issue and provide an overview of the BDD-based synthesis schemes which are available thus far. Afterwards, we propose new solutions based on a dedicated BDD optimization which aim for addressing the known shortcomings. Experimental results confirm the benefits of the proposed approach.
Keywords: Optical circuits; Synthesis; Optimization; Binary decision diagrams

Synthesis of optical circuits using binary decision diagrams - Deb, Arighna; Wille, Robert; Keszoecze, Oliver; Shirinzadeh, Saeideh; Drechsler, Rolf (Integration-The Vlsi Journal, 2017)
Keywords: Synthesis; Binary decision diagrams; Optimization; Optical circuits

Synthesis of Optical Circuits with Contradictory Optimization Objectives - Deb, Arighna; Wille, Robert; Keszocze, Oliver; Hilmich, Stefan; Drechsler, Rolf (International Workshop on Optical/Photonic Interconnects for Computing Systems, 2016)

Task-Driven Software Summarization - Binkley, Dave; Lawrie, Dawn; Hill, Emily; Burge, Janet; Harris, Ian; Hebig, Regina; Keszocze, Oliver; Reed, Karl; Slankas, John (29th IEEE International Conference on Software Maintenance, ICSM 2013, 2013)
Keywords: Task-oriented; Source code summary; Summarization evaluation

The Complexity of Error Metrics - Keszocze, Oliver; Soeken, Mathias; Drechsler, Rolf (Information Processing Letters, 2018)
Keywords: Approximate computing; Error metrics; Computational complexity

To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations - Plagwitz, Patrick; Hannig, Frank; Teich, Jürgen; Keszöcze, Oliver (2023)
Convolutional Neural Networks (CNNs) are widely employed to solve various problems, e.g., image classification. Due to their compute- and data-intensive nature, CNN accelerators have been developed as ASICs or on FPGAs. Increasing complexity of applications has caused resource costs and energy requirements of these accelerators to grow. Spiking Neural Networks (SNNs) are an emerging alternative to CNN implementations, promising higher resource and energy efficiency. The main research question addressed in this paper is whether SNN accelerators truly meet these expectations of reduced energy requirements compared to their CNN equivalents. For this purpose, we analyze multiple SNN hardware accelerators for FPGAs regarding performance and energy efficiency. We present a novel encoding scheme of spike event queues and a novel memory organization technique to improve SNN energy efficiency further. Both techniques have been integrated into a state-of-the-art SNN architecture and evaluated for MNIST, SVHN, and CIFAR-10 datasets and corresponding network architectures on two differently sized modern FPGA platforms. For small-scale benchmarks such as MNIST, SNN designs provide rather no or little latency and energy efficiency advantages over corresponding CNN implementations. For more complex benchmarks such as SVHN and CIFAR-10, the trend reverses

Towards Clause Learning a la Carte through VarMonads - Friedemann, Arved; Keszöcze, Oliver (International Symposium on Logic-based Program Synthesis and Transformation, 2022)

Towards Dynamic Execution Environment for System Security Protection against Hardware Flaws - Schmitz, Kenneth; Keszocze, Oliver; Schmidt, Jurij; Grosse, Daniel; Drechsler, Rolf (17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, 2018)
Keywords: Aho Corasick; Runtime Monitoring; QEMU

Translating between the Roots of Identity in Quantum Circuits - Castryck, Wouter; Demeyer, Jeroen; De Vos, Alexis; Keszocze, Oliver; Soeken, Mathias (48th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2018, 2018)
Keywords: Pauli groups; Group theory; Quantum computing

Using Deep Learning to Demodulate Transmissions in Molecular Communication - Bartunik, Max; Keszöcze, Oliver; Schiller, Benjamin; Kirchner, Jens (2022 IEEE 16th International Symposium on Medical Information and Communication Technology (ISMICT), 2022)

Visualizing Microfluidic Biochips Interactively - Keszocze, Oliver; Stoppe, Jannis; Wille, Robert; Drechsler, Rolf (Workshop on Design Automation for Understanding Hardware Designs, 2016)