Employing Polyhedral Methods to Optimize Stencils on FPGAs with Stencil-specific Caches, Data Reuse, and Wide Data Bursts - Mayer, Florian; Brandner, Julian; Philippsen, Michael (14th International Workshop on Polyhedral Compilation Techniques, (IMPACT 2024, in conjunction with HiPEAC 2024), 2024)
It s well known that to accelerate stencil codes on CPUs or GPUs and to exploit hardware caches and their lines optimizers must find spatial and temporal locality of array accesses to harvest data-reuse opportunities. On FPGAs there is the burden that there are no built-in caches (or only pre-built hardware descriptions for cache blocks that are inefficient for stencil codes). But this paper demonstrates that this lack is also a chance as polyhedral methods can be used to generate stencil-specific cache-structures of the right sizes on the FPGA and to fill and flush them efficiently with wide bursts during stencil execution. The paper shows how to derive the appropriate directives and code restructurings from stencil codes so that the FPGA compiler generates fast stencil hardware. Switching on our optimization improves the runtime of a set of 10 stencils by between 43× and 156×.<br

Employing polyhedral methods to optimize stencils on FPGAs with stencil-specific caches, data reuse, and wide data bursts [Reproduction Package] - Mayer, Florian; Brandner, Julian; Philippsen, Michael (2024)
This archive contains the the benchmark data and source code described in the conference paper "Employing polyhedral methods to optimize stencils on FPGAs with stencil-specific caches, data reuse, and wide data bursts" (In Proc. 14th Intl. Workshop on Polyhedral Compilation Techniques), Munich, Germany, Jan. 2024.<br

Employing Polyhedral Methods to Reduce Data Movement in FPGA Stencil Codes - Mayer, Florian; Brandner, Julian; Philippsen, Michael (Proc. of the 35rd Intl. Workshop on Languages and Compilers for Parallel Computing (LCPC 2022), 2023)
Due to the ubiquity of stencil codes in scientific computing there is a strong need to optimize their runtimes. When using a GPU as an accelerator, programmers need to amortize the cost of shipping data to/from the device. When using an FPGA as an accelerator, the situation is worse as programmers also need to build a cache-like data shipment on the device. To avoid this tedious and error-prone task, our source-to-source compiler takes OpenMP pragma-annotated stencil codes, derives a polyhedral model from them, finds and merges overlapping contiguous read accesses, and instruments the code with vendor-specific annotations that guide the FPGA synthesis to generate efficient stencil hardware with fast data shipment and fast on-FPGA cache-like structures. Our data movement optimization improves the runtime of a set of stencil codes from three different sources by between 1.3x and 5.8x, on averag

Multilayer Multipurpose Caches for OpenMP Target Regions on FPGAs - Brandner, Julian; Mayer, Florian; Philippsen, Michael (OpenMP: Advancing OpenMP for Future Accelerators, 2024)
Multipurpose caches can improve the throughput between the FPGA’s memory and the hardware that is generated when offloading OpenMP target regions. We discuss and evaluate the weaknesses (and also advantages) of different cacheing techniques in this context. Our OpenMP-to-FPGA compiler fully automatically combines and inserts them as a multilayer cache to get the best of all worlds. We evaluate on a diverse benchmark and achieve an average speedup of 3.65, outperforming 1-layer caches both in terms of runtime and resilienc

Multilayer Multipurpose Caches for OpenMP Target Regions on FPGAs [Data set] - Brandner, Julian; Mayer, Florian; Philippsen, Michael (2024)
This archive contains the benchmarks used in the conference paper "Multilayer Multipurpose Caches for OpenMP Target Regions on FPGAs" <br
Keywords: FPGA; OpenMP; target offloading; hardware cache

Multipurpose Cacheing to Accelerate OpenMP Target Regions on FPGAs (Best Paper Award) - Brandner, Julian; Mayer, Florian; Philippsen, Michael (OpenMP: Advanced Task-Based, Device and Compiler Programming, 2023)
While FPGAs can offer great throughput and energy efficiency, when offloading OpenMP target regions to them the memory bandwidth often limits the ability to exploit their potential. As a remedy, our OpenMP-to-FPGA compiler fully automatically inserts optimized multipurpose cache blocks into the generated FPGA hardware. We exploit characteristics of OpenMP target regions to both avoid costly bus snooping hardware and to achieve cache consistency. On a diverse set of benchmarks with data reuse the caches reduce the runtime by 43 % on average, while only consuming slightly more FPGA resource.
CRIS-Team Scopus Importer:2023-10-06
Keywords: FPGA; hardware cache; OpenMP; target offloading

Multipurpose Cacheing to Accelerate OpenMP Target Regions on FPGAs [Data set] - Brandner, Julian; Mayer, Florian; Philippsen, Michael (2023)
This archive contains the benchmarks used in the conference paper "Multipurpose Cacheing to accelerate OpenMP Target Regions on FPGAs" <br
Keywords: FPGA; OpenMP; target offloading; hardware cache

OpenMP on FPGAs - A Survey - Mayer, Florian; Knaust, Marius; Philippsen, Michael (OpenMP: Conquering the Full Hardware Spectrum - Proceedings of the 15th International Workshop on OpenMP (IWOMP 2019), 2019)
Due to the ubiquity of OpenMP and the rise of FPGA-based accelerators in the HPC world, several research groups have attempted to bring the two together by building OpenMP-to-FPGA compilers. This paper is a survey of the current state of the art (with a focus on the OpenMP target pragma). It first introduces and explains a design space for the compilers. Design space dimensions include how FPGA infrastructure is generated, how work is distributed, and where/how target outlining is done. A table concisely condenses the available information on the surveyed projects which are also summarized and compared. The paper concludes with possible future research directions.<br

OpenMP to FPGA Offloading Prototype using OpenCL SDK - Knaust, Marius; Mayer, Florian; Steinke, Thomas (2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2019)
Field-programmable gate arrays (FPGAs) are of great interest for future high-performance computing and data analytics systems, since they are capable of efficient, highly-parallel data processing. Even though high-level synthesis became more popular in the last years, the effort of porting existing scientific software onto FPGAs is still considerable. We propose to use OpenMP target offloading as a solution, which we implement in a first prototype, making use of the preexisting OpenCL SDK of the FPGA vendor. Early results demonstrate the feasibility of this approach and also reveal that further optimizations will be necessary such that code can be written in an FPGA-agnostic way.
Keywords: OpenMP; FPGA; offloading; heterogeneous; accelerators; reconfigurable

Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling - Brandner, Julian; Mayer, Florian; Philippsen, Michael (OpenMP in a Modern World: From Multi-device Support to Meta Programming, 2022)
Recent works aimed at expanding the target offloading capabilities of OpenMP to FPGA platforms. While enabling the easy construction of heterogeneous systems, the approach has to face a major hurdle: by blurring the line between software and hardware development, it forces software developers to consider hardware limitations. This can be difficult through the abstractions that OpenMP introduces over the generated hardware. The high level synthesis tools used by OpenMP compilers to generate hardware already offer predictions on hardware usage. Their value for OpenMP offloading however is questionable. This paper is based on the data mining we conducted on thousands of kernel variations. It demonstrates and proofs under which circumstances these predictions can be trusted in the context of OpenMP to FPGA offloading and concludes by showing how to derive runtime performance predictions from them. The model we present can be used without experience in hardware development and quickly predicts runtime on our benchmarks with an average Pearson correlation of 0.897. This knowledge allows developers to make fast, informed design decision
Keywords: FPGA; OpenMP; target offloading; data mining

Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling [Data set] - Brandner, Julian; Mayer, Florian; Philippsen, Michael (2022)
This archive contains the samples generated for the conference paper "Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling" (In Proc. 18th Intl. Workshop on OpenMP (IWOMP), Chattanooga, TN, Sept. 2022, Springer LNCS vol. 13527, pp. 94–108, https://doi.org/10.1007/978-3-031-15922-0_7

The ORKA-HPC Compiler — Practical OpenMP for FPGAs - Mayer, Florian; Brandner, Julian; Hellmann, Matthias; Schwarzer, Jesko; Philippsen, Michael (Proceedings of the 34th International Workshop on Languages and Compilers for Parallel Computing (LCPC 2021), 2022)
ORKA-HPC is a new and downloadable OpenMP-to-FPGA compiler that is easy to set up, easy to use, and easy to extend. It targets a variety of different FPGA-boards, and is distributed with a “batteries included” runtime and development environment. Starting from a set of properties that such a compiler must possess, we derive how ORKA-HPC achieves these, reason about the underlying decisions, and evaluate ORKA-HPC’s current state of development. The paper concludes with future work and provides a download link.