A 30GHz bandwidth driver amplifier with high output voltage swing for ultra-wideband localization- and sensor systems - Sewiolo, Benjamin; Rascher, Jochen; Weigel, Robert (Asia-Pacific Microwave Conference, 2008, 2008)
This paper reports on the analysis, design and characterization of a 30 GHz lumped broadband driving amplifier for ultra-wideband localization and sensor systems. The circuit integrates a cascode differential stage, which is fed by two cascaded emitter-followers (EF). The differential gain is 10 dB with a gain flatness of plusmn1 dB in the desired frequency range. This amplifier exhibits an output 1-dB compression point of 12 dBm. The maximum differential output voltage swing is 3.2 Vpp. The amplifier consumes a power of 560 mW at a supply voltage of plusmn3.3 V. The compact 0.5 mm2 amplifier is manufactured in a low-cost 0.25 mum SiGe BiCMOS technology with a transit frequency of 75 GHz.
elib2cris::1512001600,sewiolo2008c

A Classification and Comparative Overview of State-of-the-Art Analog Linearization Techniques for Integrated CMOS Power Amplifiers - Zohny, Amr; Rascher, Jochen; Fischer, Georg; Weigel, Robert; Ußmüller, Thomas (IEEE International Conference on Wireless Information Technology and Systems - ICWITS 2012, 2012)
In order to conform to the latest mobile communication standards, highly-linear power amplifiers (PA) are required. This is a challenge since high power added efficiency (PAE) is also needed for long battery life which dictates operating close to saturation where amplitude and phase nonlinearities are dominant. Thus linearization is necessary to simultaneously improve average efficiency and linearity [1]. Traditional linearization techniques such as feedback and feedforward suffer from bandwidth limitations and efficiency degradation respectively. Furthermore, digital predistortion (DPD) techniques are integrable albeit suffering from high system complexity [2]. State-of-the-art analog linearization techniques however solve many of these problems. The aim of this paper is to propose a classification of these techniques as shown in section II. In addition, section III shows a comparative overview of these techniques. Utilizing that classification and comparative study, the proper deep submicron (DSM) CMOS on-chip linearization techniques for handsets are then identified for modern communication standards.
elib2cris::1512001600,zohny2012a
Keywords: Power Amplifier; Linearity; PAE; CMOS; Predistortion

A CMOS RF Front-End IC for Multi Antenna Diversity Applications in the S-Band - Hartmann, Christian; Rascher, Jochen; Weigel, Robert; Fischer, Georg; Ußmüller, Thomas (19th International Conference on Microwaves, Radar and Wireless Communications (MIKON), 2012)
In recent years the reception of audio broadcast signals via satellite has become popular, especially in the United States with the SDARS-system, supplying high quality broadcast services in particular to customers with mobile usage scenarios like in cars. There, the problem of reception impairments due to multipath wave propagation in urban areas or influences from dense foliage of the surrounding vegetation affects the broadcast quality. A possibility to minimize signal interruptions and to enhance the reception quality is the application of fast switchable multi antenna diversity receivers. In this paper we present the concept of an integrated RF front-end IC for such a system and describe the design of several important building blocks. The circuits are implemented in a 150nm CMOS technology from LFoundry in Landshut, Germany.
elib2cris::1512001600,hartmann2012a

A Comparative Overview of High Power Handling CMOS Switches and their Recent Applications in RF Front-Ends - Rascher, Jochen; Zohny, Amr; Glock, Stefan; Fischer, Georg; Weigel, Robert; Ußmüller, Thomas (14th Annual Wireless and Microwave Technology Conference (WAMICON), 2013)
In this publication techniques for high power handling capability (PHC) of RF switches in bulk CMOS are investigated and compared. Together with high isolation approaches these allow reconfigurable power amplifiers (PAs) or radio front-ends for Watt level communication standards. Special care is taken to assess the applicability of the solutions for monolithic integration in scaled CMOS processes. Results are shown with PHC as high as 34dBm in a 32nm CMOS process. Recent applications for the switches in front-ends or reconfigurable PAs are analyzed. They show large DC current reduction in back-off with stage bypassing and load adaptation concepts. Up to 50% DC current reduction for low output power is reported. This greatly improves the average PA efficiency for varying envelope signals without the efforts of more advanced solutions like envelope tracking.
elib2cris::1512001600,rascher2013

A Comparison of State-of-the-Art Efficiency Enhancement Techniques of Fully Integrated CMOS Power Amplifiers for Handset LTE Applications - Zohny, Amr; Rascher, Jochen; Weigel, Robert; Ußmüller, Thomas (International Conference on Wireless Information Technology and Systems, 2013)
Among the significant remaining challenges of complete transceiver integration for handset applications is the implementation of high-efficiency power amplifiers (PA) in CMOS. This challenge is exacerbated by the high crest factors of the signals utilized in WCDMA and LTE standards. The first aim of this paper is to identify the shortcomings of the traditional efficiency enhancement techniques in dealing with LTE in CMOS. In addition, an investigation of state-ofthe- art implemented efficiency enhancement methods is performed. Moreover, a comparative overview of the aforementioned techniques is presented to provide guidelines for high-efficiency CMOS LTE PA. This is accomplished while identifying the bottlenecks for the future LTE upgrades. Finally, the performances of the investigated techniques for CMOS are compared with other technologies to assay the commercial suitability of CMOS PA for LTE.
elib2cris::1512001600,zohny2013
Keywords: Power amplifier; Power-added efficiency; linearity; CMOS; long-term evolution; peak-to-average power ration

A Memoryless Semi-Physical Power Amplifier Behavioral Model Based on the Correlation Between AM-AM and AM-PM Distortions - Glock, Stefan; Rascher, Jochen; Sogl, Bernhard; Ußmüller, Thomas; Müller, Jan-Erik; Weigel, Robert (IEEE Transactions on Microwave Theory and Techniques, 2015)
A new semi-physical memoryless computationally effective behavioral model (BM) capable of predicting amplitude-modulation-to-amplitude-modulation (AM-AM) and amplitude-modulation-to-phase-modulation (AM-PM) distortions is proposed. In recent years, AM-AM and AM-PM distortions have been separately studied in literature. Here, we investigate the correlation between AM-AM and AM-PM distortions first. Based on the observed correlation, a novel AM-PM model is derived from the well-known Rapp AM-AM model. On the basis of the close relationship between the AM-AM and AM-PM model, a highly accurate and computationally effective large-signal BM is obtained. The newly developed model addresses the current needs of the mobile industry that requires BMs of the power amplifier (PA), which can be interpreted by the designers. In addition, the models must be computationally effective due to the limited computation power in mobile handset. Therefore, only memoryless BMs can be taken into account and larger errors are accepted for the sake of computational effectiveness. In this paper, it is shown that the newly introduced model achieves excellent results, when it is applied to actual industrial applications of two GaAs-based class-AB PAs in 65-nm technology and one CMOS-based class AB PA in 28-nm technology, which are designed for mobile communications.
elib2cris::1512001600,glock2015

Analog Compensation of AM-AM and AM-PM effects for HighEfficiency Stacked-FET Power Amplifiers in 65-nm Standard CMOS - Zohny, Amr; Leuschner, Stephan; Rascher, Jochen; Pinarello, Sandro; Ußmüller, Thomas; Müller, Jan-Erik; Fischer, Georg; Weigel, Robert (European Microwave Integrated Circuits Conference (EuMIC), 2013)
Simultaneously achieving high linearity and high power-added efficiency (PAE) is essential for power amplifiers (PA) operating with modern communication signals. The challenge is exacerbated by the low breakdown voltages of standard CMOS realizations. This work presents a low-complexity programmable analog scheme to compensate the strong AM-AM and AM-PM nonlinearities of the high-ruggedness stacked-cascode topology while maintaining high PAE. The proposed solution utilizes standard NMOS devices to achieve peak PAE of 60% at the 900 MHz band from a 3V supply. The compensation scheme manages to improve the output 1-dB compression point by up to 2 dB and keep the AM-PM variation within 5 degrees. The proposed method improves the linear output power (@ ACPR= -40 dBc) for a Class-AB power amplifier by up to 1.5 dB without compromising PAE or saturated output power
elib2cris::1512001600,zohny2013a
Keywords: Power amplifier; Stacked FET; Stacked cascode; CMOS; linearization; ruggedness

A Novel Power Amplifier Behavioral Model for Improving the Linearity-Efficiency Tradeoff - Glock, Stefan; Rascher, Jochen; Sogl, Bernhard; Ußmüller, Thomas; Müller, Jan-Erik; Fischer, Georg; Weigel, Robert (International Microwave and RF Conference (IMaRC), 2013)
This paper focuses on a novel power amplifier (PA) semi-physical behavioral model (BM) to study the linearityefficiency trade-off in modern wireless transmitter systems. While the behavioral models known in the literature mainly focus on the precise description of the PA nonlinearity in terms of amplitudemodulation- to-amplitude-modulation (AM-AM) and amplitudemodulation- to-phase-modulation (AM-PM) distortions, the model introduced here, also predicts the DC current flowing from the power supply to the PA. This allows to optimize the battery current while keeping the out-of-channel interference within specification limits. In a case study, the DC current and the amplitude distortions of a PA, designed for IEEE 802.11b/g/n applications are predicted with a normalized mean square error (NMSE) of -39.92 dB and -47.07 dB, respectively.
elib2cris::1512001600,glock2013c

A Semi-Physical Power Amplifier Behavioral Model Capable of Predicting Gain Expansion Effects - Glock, Stefan; Rascher, Jochen; Sogl, Bernhard; Ußmüller, Thomas; Müller, Jan-Erik; Fischer, Georg; Weigel, Robert (IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications, 2014)
A novel semi-physical power amplifier (PA) behavioral model (BM) that describes the input-output characteristic of PAs exhibiting gain expansion (GE) is introduced. The accurate prediction of GE is of particular importance because GE typically improves the power added efficiency (PAE) at high input powers. Though, GE impacts the spectral regrowth. Therefore, BMs that are capable of predicting GE, like the one introduced in this work, are highly desirable. In a case study, the proposed model is employed to predict the AM-AM distortions of a GaAs PA designed for LTE applications. Excellent agreement between measurement and simulation results is obtained. The computational efficient model allows system-level simulations of advanced transmitter systems in order to optimize their modes of operation.
elib2cris::1512001600,glock2014

Highly linear robust RF switch with low insertion loss and high power handling capability in a 65nm CMOS technology - Rascher, Jochen; Pinarello, Sandro; Müller, Jan-Erik; Fischer, Georg; Weigel, Robert (2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2012)
This work reports on the considerations for building RF switches in deeply scaled CMOS. As demonstrator single pole single throw (SPST) switches in a standard 65 nm technology are designed and measured. Goal of this design is lowest insertion loss while achieving high power handling capability, linearity, and robustness. For the novel design of switch variant Dev 1 0.8dB of insertion loss, 30dBm of power handling and an input third order intermodulation intercept point (iIP3) of 48.8 dBm has been achieved at 1.8 GHz. High robustness is achieved by stacking 4 transistors. Isolation at 1.8 GHz is better than 22dB. For high power handling capability in off state a method is implemented to rise the DC voltage level at inner nodes of the switch. Thus the threshold voltage lowering in deeply scaled CMOS can be counteracted. The small and large signal behaviour of the switch is compared to conventional designs and benefits are proven.
elib2cris::1512001600,rascher2012

Integrated Reconfigurable CMOS Power Amplifiers - Rascher, Jochen; Zohny, Amr; Weigel, Robert (European Microwave Conference (EuMC), 2013)
Technologies for Embedded Wireless Systems Workshop
elib2cris::1512001600,rascher2013a

Methods for Low Insertion Loss RF Switches with Increased Power Handling Capability in 65nm CMOS - Rascher, Jochen; Pinarello, Sandro; Müller, Jan-Erik; Fischer, Georg; Weigel, Robert (Asia-Pacific Microwave Conference 2011 (APMC 2011), 2011)
This work reports on methods and dependencies for the design of low insertion loss single pole single throw (SPST) switches in 65nm CMOS with triple well transistors. Two different switch types are investigated and implemented. The series switch has less than 1dB insertion loss at 1.8GHz and a 1dB input compression point (P1dB) of 28.8dBm. The shunt switch has less than 0.4dB insertion loss at 1.8GHz and a P1dB of 29.1dBm. Isolation of the series and shunt switches at 1.8GHz is better than 21dB and 20dB, respectively. By applying a resistive body ﬂoating technique low insertion loss and increased power handling capability are achieved. At the shunt switch negative gate bias is adopted for improved P1dB. At the series switch a method is implemented to boost the DC voltage level at source/ drain nodes of transistors for improved power handling capability in off state without additional circuitry or any DC power consumption. The combination of these methods andan additional DC voltage in on state increases power handling capability in both states of the switch.
elib2cris::1512001600,rascher2011a

Phasenschieber für satellitenfunkempfänger-frontends / A phase shifter for satellite radio receiver frontends - Rascher, Jochen; Ußmüller, Thomas (GMM Fachbericht 70: ANALOG 2011, 2011)
In this publication the advantages of passive phase shifters are shown which can be used in integrated satellite radio receiver frontends at 2.3GHz center frequency. High large signal robustness, low temperature dependency, and low inser- tion loss <1dB per phase bit can be achieved. The 3 bit phase shifter design uses FET switches in resistive body floating technique for that.
elib2cris::1512001600,rascher2011

RF Switch Design for Reconfigurable Power Amplifiers with High Back-off Efficiency in nm-CMOS Technologies - Rascher, Jochen (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2015)

Simulation and Implementation Demands for State-of-the-Art Integrated Linear Power Amplifiers - Zohny, Amr; Rascher, Jochen; Weigel, Robert (Electrical and Electronic Engineering for Communication EEEfCOM 2012, 2012)
elib2cris::1512001600,zohny2012
Keywords: Linearity; Power Amplifier; CMOS; ACPR; Intermodulation

Techniques for Reconfigurable Integrated Power Amplifiers with RF Switches - Rascher, Jochen; Zohny, Amr; Weigel, Robert (Electric and Electronic Engineering for Communication Workshop (EEEfCOM), 2012)
elib2cris::1512001600,rascher2012a

Time-Efficient Adjacent Channel Power Ratio Simulation utilizing Overlap-add Signal Decomposition for UMTS Power Amplifiers - Zohny, Amr; Leuschner, Stephan; Kastner, M.; Rascher, Jochen; Ußmüller, Thomas; Müller, Jan-Erik; Fischer, Georg; Weigel, Robert (Asia-Pacific Microwave Conference - APMC 2012, 2012)
The suitability of an RF power amplifier (PA) for modern sophisticated modulation schemes demands high linearity. One of the most significant figures of merit concerning PA linearity is its adjacent channel power ratio (ACPR). The aim of this paper is to propose a time-efficient simulation procedure for ACPR which conforms with the latest 3GPP TS 25.101 specifications for its calculation. This procedure overcomes the time penalty associated with the traditional envelope-based simulation method. The approach is based on standard harmonic balance (HB) tools with MATLAB post-processing incorporating the Overlap-add (OLA) signal decomposition DSP technique for fast RRC filtering. In addition, the simulation results are compared with measurements of a commercial WCDMA PA for verification. Accuracies of better than 0.5dB and 1.1dB are achieved up to 10dB and 2dB backoff respectively.
elib2cris::1512001600,zohny2012b
Keywords: Power Amplifier; Linearity; ACPR; WCDMA; Distortion; Harmonic Balance