A flexible mixed-signal image processing pipeline using 3D chip stacks - Shi, Lan; Söll, Christopher; Pfundt, Benjamin; Bänisch, Andreas; Reichenbach, Marc; Seiler, Jürgen; Ussmueller, Thomas; Weigel, Robert (Journal of Real-Time Image Processing, 2016)
This work presents a highly flexible mixed-signal CMOS image sensor suitable for smart camera applications. These systems need to fit different constraints regarding power consumption, speed and quality, and the optimal compromise may differ depending on the application. Moreover, the best implementation of a desired image processing task may be in the analog or the digital domain, or even a combined computation. Different aspects starting from the image sensor and signal acquisition up to the pre-processing in analog and digital domain are investigated in this paper to optimize not just one part of the system, but the whole system altogether. Moreover, it is shown that analog processing algorithms can improve signal quality, processing speed and latency while being able to save power, which is important for real-time systems. In order to be able to carry out spatial operations, the state-of-the-art sensor is modified to be able to read out multiple pixels at the same time. This allows analog spatial filter operations which consume significantly less power. As an example, an averaging filter is described which needs less than 5.3 % of the power–time product of a digital implementation for one computation. To enhance data throughput and flexibility, 3D chip stacking is proposed to partition the sensor in smaller units and enable massively parallel processin
Keywords: 3D chip stacking; Analog pre-processing; Application optimized image pipeline; Partitioning; Smart camera

A New Virtual Hardware Laboratory for Remote FPGA Experiments on Real Hardware - Reichenbach, Marc; Schmidt, Michael; Pfundt, Benjamin; Fey, Dietmar (Proceedings of the 2011 International Conference on E-Learning, E-Business, Enterprise Information Systems, &E-Goverment, 2011)
UnivIS-Import:2015-04-16:Pub.2011.tech.IMMD.IMMD3.anewvi
Keywords: E-Learning; Virtual Laboratory; FPGA Design; Remote Experiments; Circuit Design

An Image Processing Operator Language for Design and Synthesis of Smart Camera Architectures - Hartmann, Christian; Häublein, Konrad; Pfundt, Benjamin; Reichenbach, Marc; Fey, Dietmar (Mitteilungen - Gesellschaft für Informatik e.V., 2017)
UnivIS-Import:2017-07-10:Pub.2017.tech.IMMD.IMMD3.animag

Comprehensive curriculum for reconfigurable heterogeneous computer architecture education - Pfundt, Benjamin; Reichenbach, Marc; Fey, Dietmar (IET Circuits Devices & Systems, 2017)
UnivIS-Import:2018-09-05:Pub.2017.tech.IMMD.IMMD3.compre

Designing and Manufacturing of Real Embedded Multi-Core CPUs: A Holistic Teaching Approach in Computer Architecture - Reichenbach, Marc; Pfundt, Benjamin; Fey, Dietmar (Proceedings of the Tenth Workshop on Microelectronics Education, 2014)
How to teach students current computer architecture? This is an important question in our modern world, where the market of embedded parallel processors is continuously growing. In every compact device today, such as smart phones and tablets, small and powerful multi-core architectures are present. Therefore, there is the need to teach students the whole range of embedded design - starting from the basics of computer architecture through to real chip design. In this paper, we present our experience with a holistic teaching approach in embedded multi-core computing, which covers most aspects of embedded system design. Beginning with the theoretical foundations of computer architecture, a custom multi-core CPU is designed by teams of students and finally transferred to a complete IC layout. As a distinctive feature, the layout is manufactured and packaged. The students will get their own processor chip, which they can test and evaluate. Student surveys show that the students are highly motivated to obtain the opportunity to produce their own chip. This results in active participation in the lessons/seminars and the training of valuable social skills. © 2014 IEEE.
UnivIS-Import:2015-04-16:Pub.2014.tech.IMMD.IMMD3.design
Keywords: CPU design; embedded computing education; IC design; multi-core; teaching computer architecture

Design of a Programmable Architecture for Cellular Automata Based Image Processing for Smart Camera Chips - Reichenbach, Marc; Seidler, Ralf; Fey, Dietmar; Pfundt, Benjamin (Proc. of the Annual International Conference on Advances in Distributed and Parallel Computing (ADPC 2010), 2010)
UnivIS-Import:2019-08-15:Pub.2010.tech.IMMD.IMMD3.design

Fast image processing for optical metrology utilizing heterogeneous computer architectures - Reichenbach, Marc; Seidler, Ralf; Pfundt, Benjamin; Fey, Dietmar (Computers & Electrical Engineering, 2013)
UnivIS-Import:2015-03-09:Pub.2013.tech.IMMD.IMMD3.fastim

Framework for Parameter Analysis of FPGA-based Image Processing Architectures - Reichenbach, Marc; Pfundt, Benjamin; Fey, Dietmar (Proceedings of International Conference on Systems, Architectures, MOdeling and Simulation (SAMOS), 2015)
UnivIS-Import:2015-10-26:Pub.2015.tech.IMMD.IMMD3.framew
Keywords: GRK-1773

Generic Emergent Computing in Chip Architectures - Reichenbach, Marc; Seidler, Ralf; Fey, Dietmar; Pfundt, Benjamin (Organic Computing - A Paradigm Shift for Complex Systems, 2011)
UnivIS-Import:2019-03-25:Pub.2011.tech.IMMD.IMMD3.generi
Keywords: cellular array processing; smart camera chips; marching pixels; parallel embedded systems

Novel Image Processing Architecture for 3D Integrated Circuits - Pfundt, Benjamin; Reichenbach, Marc; Fey, Dietmar; Söll, Christopher (Parallel -Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS), 2015)
Utilizing highly parallel processors for high speed embedded image processing is a well known approach. However, the question of how to provide a sufficiently fast data rate from image sensor to processing unit is still not solved. As Trough-Silicon-Vias (TSV), a new technology for chip stacking, become available, parallel image transmission from the image sensor to processing unit is enabled. Nevertheless, the usage of a new technology requires architectural changes in the processing units.With this technology at hand, we present a novel image preprocessing architecture suitable for image processing in 3D chips stacks. The architecture was developed in parallel with a customized image sensor to make a real assembly possible. It is fully functionally verified and layouted for a 150 nm process. Our performance estimation shows a processing speed of 770 up to 30.000 fps (frames per second) for 5x5 filters.
elib2cris::1512001600,pfundt2015
Keywords: 3D IC; TSV; parallel processing; 2D filters; full buffering

Smart Sensor Architectures for Embedded Biosignal Analysis - Pfundt, Benjamin; Reichenbach, Marc; Eskofier, Björn; Fey, Dietmar (Proceedings of the 2013 Conference on Design & Architectures for Signal & Image Processing, 2013)
In many sports and medical applications small and wearable sensors are used that capture motion and physiological signals. Yet, commonly such sensor are only capable of acquiring raw data, which is afterwards transmitted to a smartphone or other mobile computing device where processing and classification is carried out. This results in limited usability because another device has to be worn. Moreover, high power consumption due to continuous transmission is a main disadvantage. Therefore, we propose a smart sensor approach that can alleviate these problems by carrying out the processing on the sensor itself. To house the processing schemes in the sensor node we developed a new computer architecture utilizing an FPGA and an ASIC. To show the benefits of the in-sensor processing, we chose two representative biosensor applications: a movement and fall detection system for the elderly and a swimming style recognition system for professional athletes. Compared to conventional approaches the same classification rate can be achieved while saving space, power, weight and setup costs.
UnivIS-Import:2015-04-16:Pub.2013.tech.IMMD.IMMD3.smarts
Keywords: biosignal processing; smart sensors; FPGA; ASIC

Smart Sensor Framework: A Pressure Sensor for Smart Home Applications - Lieske, Tobias; Schuklin, Dennis; Hohnloser, Daniel; Reichenbach, Marc; Pfundt, Benjamin; Fey, Dietmar; Weigel, Robert (1. E|HOME-CENTER SYMPOSIUM, 2016)

System on Chip Generation for Multi-Sensor and Sensor Fusion Applications - Lieske, Tobias; Pfundt, Benjamin; Vaas, Steffen; Reichenbach, Marc; Fey, Dietmar (Proceedings of the 17th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2017)
UnivIS-Import:2017-12-18:Pub.2017.tech.IMMD.IMMD3.system

Teaching Heterogeneous Computer Architectures Using Smart Camera Systems - Pfundt, Benjamin; Reichenbach, Marc; Hartmann, Christian; Häublein, Konrad; Fey, Dietmar (Proceedings of the 11th Workshop on Microelectronics Education, 2016)
UnivIS-Import:2016-06-01:Pub.2016.tech.IMMD.IMMD3.teachi
Keywords: GRK-1773