A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs - Knödtel, Johannes; Schwabe, Wolffhardt; Lieske, Tobias; Reichenbach, Marc; Fey, Dietmar (2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2018)
System designers often face a serious challenge when estimating the energy requirements of their system. This information is essential for the design process. Especially for IP blocks, this is hard to estimate, since the influence of the surrounding system on the IP block needs to be considered. This creates need for a multi-level simulation: The system level must be simulated in conjunction with the IP core which is at gate level. Common approaches to this problem are too low-level and slow for system design. This paper shows another method: Using transpilation from netlists to a system design language, one can generate high-level modules which simulate the logic of the IP block and collect statistics about the energy consumption at runtime, using a statistically trained energy model. This has the advantage that no external tooling or complicated setups for crossing the boundary from system-level simulation to gate-level simulation are necessary. Benchmarks show that this approach, while rather simple to implement, yields energy values much closer to the ones we obtained with a professional gate-level toolchain than with simple average case figures, when evaluated with real world stimuli.
Keywords: Logic gates; IP networks; Estimation; Energy consumption; Integrated circuit modeling; Tools; System analysis and design; system-level simulation; gate-level simulation; energy estimation; hardware design

Dataflow Optimization for Programmable Embedded Image Preprocessing Accelerators - Lieske, Tobias; Reichenbach, Marc; Ringlein, Burkhard; Fey, Dietmar (Proceedings of ReConFig' 16, 2016)
UnivIS-Import:2017-12-18:Pub.2016.tech.IMMD.IMMD3.datafl
Keywords: Complexity theory; Computer architecture; Hardware; Image processing; Pipeline processing; Program processors; ADL; Dataflow Optimization; Image Processing Architectures; Parallel Processing; Pipelining

Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications - Lieske, Tobias; Uhring, Wilfried; Dumas, Norbert; Skilitsi, Anastasia Ioanna; Leonard, Jérémie; Fey, Dietmar (Journal of Signal Processing Systems, 2018)

Embedded Fluorescence Lifetime Determination for High Throughput Real-Time Droplet Sorting with Microfluidics - Lieske, Tobias; Uhring, Wilfried; Dumas, Norbert; Leonard, Jérémie; Fey, Dietmar (Proceedings of 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2017)
UnivIS-Import:2017-12-18:Pub.2017.tech.IMMD.IMMD3.embedd

FAUPU - A Design Framework for the Development of Programmable Image Processing Architectures - Reichenbach, Marc; Lieske, Tobias; Vaas, Steffen; Häublein, Konrad; Fey, Dietmar (Proceedings of ReConFig' 15, 2015)
UnivIS-Import:2017-12-18:Pub.2015.tech.IMMD.IMMD3.faupua

Heterogeneous Computing Utilizing FPGAs - Reichenbach, Marc; Holzinger, Philipp; Häublein, Konrad; Lieske, Tobias; Blinzer, Paul; Fey, Dietmar (Journal of Signal Processing Systems, 2018)
Heterogeneous computing plays an ever-increasing role in power-efficient, high-performance embedded systems for various data processing tasks, such as computer vision. One possibility to accelerate this kind of application is the usage of FPGAs as a co-processor for standard CPUs. Although hardware design is becoming easier by utilizing High-Level-Synthesis tools, the question of interfacing FPGAs and CPUs has yet to be completely solved. The Heterogeneous System Architecture (HSA) Foundation defines and publishes architecture neutral standards for heterogeneous systems and programming models. While compatible CPU, GPU and DSP designs exist, FPGA models have not been defined yet. This paper describes the IP library LibHSA, which greatly simplifies integration of domain specific FPGA acceleration into existing HSA compliant systems. It allows FPGA based accelerators to take immediate advantage of high-level language tool chains. Including user space memory access, low-latency task dispatch and other benefits of the HSA programming model. We will demonstrate LibHSA with a programmable image processor implementation on a Xilinx FPGA. The image processor supports low-level algorithms, e.g. Sobel, Median, Laplace, or Gaussian. Our results show that the LibHSA infrastructure greatly simplifies the effort integrating FPGAs and customized hardware into existing accelerator systems, runtimes and application software.

High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States - Biglari, Mehrdad; Lieske, Tobias; Fey, Dietmar (Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018)

LibHSA: One Step Towards Mastering the Era of Heterogeneous Hardware Accelerators using FPGAs - Reichenbach, Marc; Holzinger, Philipp; Häublein, Konrad; Lieske, Tobias; Blinzer, Paul; Fey, Dietmar (2017 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2017)
Various signal and image processing applications require vast acceleration in order to enable real-time processing and meet constraints in power consumption. On FPGAs these applications can be implemented as application-specific circuit. Although IP cores for various applications exist, even interfacing these usually requires experienced knowledge in hardware design. Using FPGAs or other accelerators in a heterogeneous system from a host CPU would simplify the usage of accelerator hardware for a common software developer. Recognizing this, several companies and partners from academia created the HSA Foundation (Heterogeneous System Architecture Foundation) to define a platform specification for heterogeneous system requirements as a macro-architecture for efficient and easy targeting heterogeneous processors from popular high-level languages like C/C++, Python, Java and other domain specific languages.In this paper we present an IP library (LibHSA), that greatly simplifies integration of hardware accelerator functions into existing HSA compliant systems. This allows accelerators to take advantage of the existing HSA programming model, libraries, compilers and toolchains. We will demonstrate the work of LibHSA utilizing a programmable image processor implementation on a Xilinx FPGA. The image processor supports low-level algorithms, e.g. Sobel, Median, Laplace, or Gauss. Our results show a substantial decrease integrating customized hardware accelerators using the LibHSA infrastructure. To our knowledge, our library is the first approach for integrating reconfigurable hardware into an HSA compliant system.
Keywords: Heterogeneous System Architectures; HSA; Hardware Accelerator; Image Processing; FPGA

Multi-Level Memristive Voltage Divider: Programming Scheme Trade-offs - Lieske, Tobias; Biglari, Mehrdad; Fey, Dietmar (Proceedings of the International Symposium on Memory Systems, 2018)

Reducing Hibernation Energy and Degradation in Bipolar ReRAM-Based Non-Volatile Processors - Biglari, Mehrdad; Lieske, Tobias; Fey, Dietmar (IEEE Transactions on Nanotechnology, 2019)
Keywords: Non-volatile flip-flop; non-volatile processor; ReRAM; hibernation energy; endurance; degradation

Smart Sensor Framework: A Pressure Sensor for Smart Home Applications - Lieske, Tobias; Schuklin, Dennis; Hohnloser, Daniel; Reichenbach, Marc; Pfundt, Benjamin; Fey, Dietmar; Weigel, Robert (1. E|HOME-CENTER SYMPOSIUM, 2016)

System on Chip Generation for Multi-Sensor and Sensor Fusion Applications - Lieske, Tobias; Pfundt, Benjamin; Vaas, Steffen; Reichenbach, Marc; Fey, Dietmar (Proceedings of the 17th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2017)
UnivIS-Import:2017-12-18:Pub.2017.tech.IMMD.IMMD3.system