Acceleration of multiresolution imaging algorithms: A comparative study - Membarth, Richard; Kutzer, Philip; Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2009)
In this paper we consider a multiresolution filter and its realization on the Cell BE and GPUs. We not only present common and specific optimization strategies undertaken for obtaining maximum performance on these architectures, but also how to obtain a speedup of 6.57x and 33.24x compared to an optimized OpenMP baseline implementation. Furthermore, we also undertake automated configuration space exploration of different partitioning possibilities for selection of best tiling parameters. © 2009 IEEE.

A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing - Dutta, Hritam; Hannig, Frank; Heigl, Benno; Hornegger, Heinz; Teich, Jürgen (Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors, 2006)
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imaging, which falls in the class of 2D adaptive filter algorithms. In this paper, we propose a semi-automatic mapping methodology for the generation of hardware accelerators for such a generic class of adaptive filtering applications in image processing. The final architecture deliver similar synthesis results as a hand-tuned design. © 2006 IEEE.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.adesig

A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (2006)

A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors - Dutta, Hritam; Kissler, Dmitrij; Hannig, Frank; Kupriyanov, Olexiy; Teich, Jürgen; Pottier, Bernard (Microprocessors and Microsystems, 2009)
New standards in signal, multimedia, and network processing for embedded electronics are characterized by computationally intensive algorithms, high flexibility due to the swift change in specifications. In order to meet demanding challenges of increasing computational requirements and stringent constraints on area and power consumption in fields of embedded engineering, there is a gradual trend towards coarse-grained parallel embedded processors. Furthermore, such processors are enabled with dynamic reconfiguration features for supporting time- and space-multiplexed execution of the algorithms. However, the formidable problem in efficient mapping of applications (mostly loop algorithms) onto such architectures has been a hindrance in their mass acceptance. In this paper we present (a) a highly parameterizable, tightly coupled, and reconfigurable parallel processor architecture together with the corresponding power breakdown and reconfiguration time analysis of a case study application, (b) a retargetable methodology for mapping of loop algorithms, (c) a co-design framework for modeling, simulation, and programming of such architectures, and (d) loosely coupled communication with host processor. © 2008 Elsevier B.V. All rights reserved.
UnivIS-Import:2015-04-14:Pub.2009.tech.IMMD.inform.aholis
Keywords: Architecture/compiler co-design; Coarse-grained embedded parallel processors; Communication; Mapping of loop programs; Reconfiguration

A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation - Teich, Jürgen; Hannig, Frank; Ruckdeschel, Holger; Dutta, Hritam; Kissler, Dmitrij; Stravet, Andrej (Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2007)

Automatic FIR Filter Generation for FPGAs - Dutta, Hritam; Hannig, Frank; Teich, Jürgen; et al. (In Proceedings of the 5th International Workshop on Embedded Computer Systems, Architectures, Modeling, and Simulation (SAMOS 2005), 2005)
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. PARO is a design system project for modeling, transformation, optimization, and synthesis of massively parallel VLSI architectures. The FIR filter generator employs during the design flow the following advanced transformations, (a) hierarchical partitioning in order to balance the amount of local memory with external communication, and (b), partial localization to achieve higher throughput and smaller latencies. Furthermore, our filter generator allows for design space exploration to tackle trade-offs in cost and speed. Finally, synthesizable VHDL code is generated and mapped to an FPGA, the results are compared with a commercial filter generator. © Springer-Verlag Berlin Heidelberg 2005.
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.automa_0

Co-Design of Massively Parallel Embedded Processor Architectures - Dutta, Hritam; Hannig, Frank; Kupriyanov, Olexiy; Teich, Jürgen; Schaffer, Rainer; Siegel, Sebastian; Merker, Renate; Keryell, Ronan; Pottier, Bernard; Chillet, Daniel; Ménard, Daniel; Sentieys, Olivier (Proceedings of the first ReCoSoC Workshop, 2005)
UnivIS-Import:2015-04-16:Pub.2005.tech.IMMD.inform.codesi

Controller Synthesis for Mapping Partitioned Programs on Array Architectures - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Proceedings of the 19th International Conference on Architecture of Computing Systems, 2006)
Processor arrays can be used as accelerators for a plenty of dataflow-dominant applications. Innately these applications have almost no control flow, but the application of sophisticated partitioning and scheduling techniques in order to handle large scale problems and to balance local memory requirements with I/O-bandwidth has the disadvantage of a more complex control flow. Thus, efficient control path synthesis is one of the greatest challenges when compiling algorithms onto processor arrays. This paper presents an efficient methodology for the automated control path synthesis for the mapping of partitioned algorithms onto processor arrays. The major advantages observed in the presented methodology are seen in, (a) control generation for different partitioning techniques and arbitrary parallelepiped tiles, (b) combined use of a global and a local control strategy in order to reduce the control overhead, (c) up to 90 percent reduction in control path area and resources compared to existing approaches. © Springer-Verlag Berlin Heidelberg 2006.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.contro

Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (2005)

Domain-Specific Reconfigurable MPSoC-Systems - Challenges and Trends - Dutta, Hritam; Hannig, Frank; Kissler, Dmitrij; Teich, Jürgen; et al. (Friday Workshop Reconfigurable Hardware, Design, Automation and Test in Europe, 2008)
UnivIS-Import:2017-12-18:Pub.2008.tech.IMMD.inform.domain

Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays - Dutta, Hritam; Hannig, Frank; Ruckdeschel, Holger; Teich, Jürgen (Journal of Systems Architecture, 2007)
Processor array architectures are optimal platforms for computationally intensive applications. Such architectures are characterized by hierarchies of parallelism and memory structures, i.e. processor arrays apart from different levels of cache have a large number of processing elements (PE) where each PE can further contain sub-word parallelism. In order to handle large scale problems, balance local memory requirements with I/O-bandwidth, and use different hierarchies of parallelism and memory, one needs a sophisticated transformation called hierarchical partitioning. Innately the applications are data flow dominant and have almost no control flow, but the application of hierarchical partitioning techniques has the disadvantage of a more complex control flow. In a previous paper, the authors presented first time a methodology for the automated control path synthesis for the mapping of partitioned algorithms onto processor arrays. However, the control path contained complex multiplication and division operators. In this paper, we propose a significant extension to the methodology which reduces the hardware cost of the global controller and memory address generators by avoiding these costly operations. © 2006 Elsevier B.V. All rights reserved.
UnivIS-Import:2015-03-09:Pub.2007.tech.IMMD.inform.effici

Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors - Membarth, Richard; Hannig, Frank; Dutta, Hritam; Teich, Jürgen (Proceedings of the 9th International Workshop on Systems, Architectures,Modeling, and Simulation (SAMOS), 2009)
In the last decade, there has been a dramatic growth in research and development of massively parallel commodity graphics hardware both in academia and industry. Graphics card architectures provide an optimal platform for parallel execution of many number crunching loop programs from fields like image processing, linear algebra, etc. However, it is hard to efficiently map such algorithms to the graphics hardware even with detailed insight into the architecture. This paper presents a multiresolution image processing algorithm and shows the efficient mapping of this type of algorithms to the graphics hardware. Furthermore, the impact of execution configuration is illustrated and a method is proposed to determine the best configuration offline in order to use it at run-time. Using CUDA as programming model, it is demonstrated that the image processing algorithm is significantly accelerated and that a speedup of up to 33x can be achieved on NVIDIA's Tesla C870 compared to a parallelized implementation on a Xeon Quad Core. © 2009 Springer Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.effici_0

Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards - Membarth, Richard; Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Transactions on High-Performance Embedded Architectures and Compilers V, 2019)
UnivIS-Import:2015-04-20:Pub.2011.tech.IMMD.inform.effici

Hierarchical Partitioning for Piecewise Linear Algorithms - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering, 2006)
Processor arrays are used as accelerators for plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor array architectures has lead to demand for mapping tools to realize the full potential of these architectures. Such architectures are characterized by hierarchies of parallelism and memory structures, i.e. processor array apart from different levels of cache arrays have a number of processing elements (PE) where each PE can further contain sub-word parallelism. In order to handle large scale problems, balance local memory requirements with I/O-bandwidth, and use different hierarchies of parallelism and memory, one needs a sophisticated transformation called hierarchical partitioning. In this paper, we introduce for the first time a detailed methodology encompassing hierarchical partitioning. © 2006 IEEE.
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.hierar

Impact of loop tiling on the controller logic of acceleration engines - Dutta, Hritam; Zhai, Jiali; Hannig, Frank; Teich, Jürgen (Proceedings of 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), 2009)
High computational effort in modern signal and image processing applications often demands for special purpose accelerators in a system on chip (SoC). New high level synthesis methodologies enable the automated design of such programmable or non-programmable accelerators. Loop tiling is a widely used transformation in such methodologies for dimensioning of such accelerators in order to match inherent massive parallelism of considered algorithms with available functional units and processor elements. Innately, the applications are data-flow dominant and have almost no control flow, but the application of tiling techniques has the disadvantage of a more complex control and communication flow. In this paper, we present a methodology for the automatic generation of the control engines of such accelerators. The controller orchestrates the data transfer and computation. The effect of tiling on area, latency, and power overhead of the controller is studied in detail. It is shown that the controller has a substantial overhead of up to 50% in for different tiling and throughput parameters. The energy-delay product is also used as a metric for identifying optimal accelerator designs. © 2009 IEEE.

Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines - Dutta, Hritam; Zhai, Jiali; Hannig, Frank; Teich, Jürgen (Proceedings of the 20th IEEE International Conference on Application-specific Systems, Architectures, and Processors, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.impact

Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (International Journal of Embedded Systems, 2006)
UnivIS-Import:2015-03-09:Pub.2006.tech.IMMD.inform.mappin_3

Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays – Architectural Parameters and Methodology - Hannig, Frank; Dutta, Hritam; Teich, Jürgen (International Journal of Embedded Systems, 2006)
Existing compilation techniques for coarse-grained reconfigurable arrays are closely related to approaches from the DSP world. These approaches employ several loop transformations, like pipelining or temporal partitioning, but they are not able to exploit the full parallelism of a given algorithm and the computational potential of a typical 2-dimensional array. In this paper, - we present an overview of constraints which have to be considered when mapping applications to coarse-grained reconfigurable arrays - we present our design methodology for mapping regular algorithms onto massively parallel arrays which is characterised by loop parallelisation in the polytope model - in a first case study, we adapt our design methodology for targeting reconfigurable arrays. The case study shows that the presented regular mapping methodology may lead to highly efficient implementations taking into account the constraints of the architectur
UnivIS-Import:2015-03-09:Pub.2004.tech.IMMD.inform.mappin_2

Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Proceedings of the 6th International Heinz Nixdorf Symposium, New Trends in Parallel & Distributed Computing, 2006)
UnivIS-Import:2015-04-16:Pub.2006.tech.IMMD.inform.mappin

Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays – Constraints and Methodology - Hannig, Frank; Dutta, Hritam; Teich, Jürgen (Proceedings of the 18th International Parallel and Distributed Processing Symposium, 2004)
Apart from academic, recently more and more commercial coarse-grained reconfigurable arrays have been developed. Computational intensive applications from the area of video and wireless communication seek to exploit the computational power of such massively parallel SoCs. Conventionally, DSP processors are used in the digital signal processing domain. Thus, the existing compilation techniques are closely related to approaches from the DSP world. These approaches employ several loop transformations, like pipelining or temporal partitioning, but they are not able to exploit the full parallelism of a given algorithm and the computational potential of a typical 2-dimensional array. In this paper, (i) we present an overview of constraints which have to be considered when mapping applications to coarse-grained reconfigurable arrays, (ii) we present our design methodology for mapping regular algorithms onto massively parallel arrays which is characterized by loop parallelization in the polytope model, and (iii), in a first case study, we adapt our design methodology for targeting reconfigurable arrays. The case study shows that the presented regular mapping methodology may lead to highly efficient implementations taking into account the constraints of the architecture.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.mappin

Massively Parallel Processor Architectures: A Co-design Approach - Dutta, Hritam; Hannig, Frank; Kupriyanov, Olexiy; Kissler, Dmitrij; Teich, Jürgen; Schaffer, Rainer; Siegel, Sebastian; Merker, Renate; Pottier, Bernard (Proceedings of the 3rd International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC), 2007)

Model-based synthesis and optimization of static multi-rate image processing algorithms - Keinert, Joachim; Dutta, Hritam; Hannig, Frank; Haubelt, Christian; Teich, Jürgen (Proceedings of Design, Automation and Test in Europe (DATE 2009), 2009)
High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special purpose architectures in form of FPGAs or ASICs. However, their efficient implementation is still a challenge, as the design complexity causes exploding development times and costs. This paper presents a new design flow which permits to specify, analyze, and synthesize complex image processing algorithms. A novel buffer requirement analysis allows exploiting possible tradeoffs between required communication memory and computational logic for multi-rate applications. The derived schedule and buffer results are taken into account for resource optimized synthesis of the required hardware accelerators. Application to a multi-resolution filter shows that buffer analysis is possible in less than one second and that scheduling alternatives influence the required communication memory by up to 24% and the computational resources by up to 16%. © 2009 EDAA.

Modeling and synthesis of communication subsystems for loop accelerator pipelines - Dutta, Hritam; Hannig, Frank; Schmid, Moritz; Keinert, Joachim (Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), 2010)
The communication synthesis for data transfer and synchronization between loop accelerators is a major challenge in streaming applications. The complexity of the problem arises from the fact that optimal memory mapping and address generation in communication subsystems for parallel data access and out-of-order communication depend on tiling and scheduling choices. This paper solves the problem of communication synthesis by leveraging the windowed synchronous data flow (WSDF) model for communication synthesis. In this context, an intermediate representation of communicating loops in the polyhedral model and a unified methodology for their projection onto the WSDF model is proposed. Finally, we present the architecture template, synthesis methodology, and overhead of the communication primitive. © 2010 IEEE.

Optimization Flow for Algorithm Mapping on Graphics Cards - Membarth, Richard; Hannig, Frank; Dutta, Hritam; Teich, Jürgen (Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.optimi

Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning - Hannig, Frank; Dutta, Hritam; Teich, Jürgen (Proceedings of the 22nd International Conference on Architecture of Computing Systems, 2009)
State-of-the-art behavioral synthesis tools barely have high-level transformations in order to achieve highly parallelized implementations. If any, they apply loop unrolling to obtain a higher throughput. In this paper, we employ the PARO behavioral synthesis tool which has the unique ability to perform both loop unrolling or loop partitioning. Loop unrolling replicates the loop kernel and exposes the parallelism for hardware implementation, whereas partitioning tiles the loop program onto a regular array consisting of tightly coupled processing elements. The usage of the same design tool for both the variants enables for the first time, a quantitative evaluation of the two approaches for reconfigurable architectures with help of computationally intensive algorithms selected from different benchmarks. Superlinear speedups in terms of throughput are accomplished for the processor array approach. In addition, area and power cost are reduced. © 2009 Springer Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.parall

PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications - Hannig, Frank; Ruckdeschel, Holger; Dutta, Hritam; Teich, Jürgen (Proceedings of the Fourth International Workshop on Applied Reconfigurable Computing, 2008)
In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications. Key features of PARO are: (1) The design entry in form of a compact and intuitive functional programming language which allows highly parallel implementations. (2) Advanced partitioning techniques are applied in order to balance the trade-offs in cost and performance along with requisite throughputs. This is obtained by distributing computations onto an array of tightly coupled processor elements. (3) We demonstrate the performance of the FPGA synthesized hardware with several selected algorithms from different benchmarks. © 2008 Springer-Verlag Berlin Heidelber
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.parosy

Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis - Dutta, Hritam; Hannig, Frank; Teich, Jürgen (Proceedings of the 22nd International Conference on Architecture of Computing Systems, 2009)
In order to meet demanding challenges of increasing computational requirements and stringent power constraints, there is a gradual trend towards heterogeneous multi-processor system-on-chip (MPSoC) designs integrating application specific acceleration engines. One major problem faced by the design tools for mapping of algorithms onto MPSoC architectures is the dimensioning of system components through performance analysis. In this paper, we propose a fast and accurate methodology for rate matching of statically scheduled acceleration engines using modular performance analysis. Given a set of Pareto-optimal hardware accelerator designs and an input workload behavior, the proposed methodology determines cost efficient hardware accelerators that can handle the workload. A motion JPEG case study illustrates the benefit of coupling high level synthesis tools with performance analysis. © 2009 Springer Berlin Heidelberg.
UnivIS-Import:2015-04-16:Pub.2009.tech.IMMD.inform.perfor

Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices - Dutta, Hritam; Hannig, Frank; Ruckdeschel, Holger; Teich, Jürgen (Proceedings of the 2nd HiPEAC Workshop on Reconfigurable Computing, 2008)
UnivIS-Import:2015-04-16:Pub.2008.tech.IMMD.inform.quanti_0

Regular Mapping for Coarse-grained Reconfigurable Architectures - Hannig, Frank; Dutta, Hritam; Teich, Jürgen (Proceedings of the 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004)
Similar to programmable devices such as processors or micro controllers also reconfigurable logic devices can be built as software, by programming the configuration of the device. In this paper, we present an overview of constraints which have to be considered when mapping applications to coarse-grained reconfigurable architectures. The application areas of most of these architectures addressing computational-intensive algorithms like video and audio processing or wireless communication. Therefore, reconfigurable arrays are in direct competition with DSP processors which are traditionally used for digital signal processing. Hence, existing mapping methodologies are closely related to approaches from the DSP world. They try to employ pipelining and temporal partitioning but they do not exploit the full parallelism of a given algorithm and the computational potential of typically 2-dimensional arrays. We present a first case study for mapping regular algorithms onto reconfigurable arrays by using our design methodology which is characterized by loop parallelization in the polytope model. The case study shows that our regular mapping methodology may lead to highly efficient implementations taking the constraints of the architecture into account.
UnivIS-Import:2015-04-16:Pub.2004.tech.IMMD.inform.regula

Synthesis and Exploration of Loop Accelerators for Systems-on-a-Chip - Dutta, Hritam (Friedrich-Alexander-Universität Erlangen-Nürnberg, 2011)