A Novel Approach to Entirely Integrate Virtual Test into Test Development Flow - Lu, Ping; Glaser, Daniel; Uygur, Gürkan; Helmreich, Klaus (Proceedings, 2009)
In this paper, we present an open architecture Virtual Test Environment (VTE) which can be easily integrated into various modularized Automatic Test Systems (ATS) compliant to Open Standard Architecture (OSA). The focus of this paper is to analyze and address the major issues that still prevent the application of Virtual Test (VT) from day-to-day's practice. As a pilot demonstration, a VHDLAMS based VTE is established and an ADC test is performed. The environment is intended to seamlessly interoperate with the test system during test program development procedure. © 2009 EDAA.
UnivIS-Import:2015-04-16:Pub.2009.tech.IE.c3scha.anovel
Keywords: ATML; Hardware description language; IEEE1641; Simulation; Test generation; VHDL; Virtual Test

Bridge the Gap between Simulation and Test: An OSA-Compliant Virtual Test Environment - Lu, Ping; Glaser, Daniel; Weichslgartner, Susanne; Uygur, Gürkan; Helmreich, Klaus; Lechner, Armin (Proceedings, 2009)
Virtual Test (VT) is a promising technique that facilitates test development and cuts time-to-market especially for analog/mixed-signal/RF devices. While the concept has been around for more than a decade and its benefits are widely acknowledged, to date it has not become a standard technique in the day-to-day business of test development. The major difficulties are: weak integration between test environment and simulation environment, lack of flexible and sophisticated simulation library for test resource and insufficient simulation efficiency. The paper discusses solutions for addressing the gaps and presents a platform independent - yet easy integrateable Virtual Test Environment (VTE). It is achieved by following steps: first, OSA-compliance - using industry standards with wide acceptance including data format, service API and protocols to pave the way for easy integration. Second, achieving interaction with the test program by modeling test resources with software control interface, this allows simulation models to be dynamically assembled together and exchanging information with the test program during run-time. At last, modeling optimization - the models of test resources in our VTE have different abstraction levels supporting both static and dynamic assembly during dynamic test program execution. Analysis is performed with respect to accuracy vs. efficiency during model assembling phase to cut computational burden. In the end, a seamless integration of VT approach into test development flow is explained. ©2009 IEEE.
UnivIS-Import:2015-04-16:Pub.2009.tech.IE.c3scha.bridge

Mixed-Signal Test Development using Open Standard Modeling and Description Languages - Lu, Ping; Glaser, Daniel; Uygur, Gürkan; Weichselgartner, Susanne; Helmreich, Klaus; Lechner, Armin (Proceedings, 2009)
A novel virtual platform is presented, providing CAD/CAT support for efficient test development and attempting to bridge the gap between design and test. The platform, which models and simulates the entire test environment, provides methodologies, model libraries and tool sets to enable design, debug and verification of all test relevant processes including fault analysis, test algorithm, load board and test program development concurrently with IC design and fabrication phase and later smoothly apply the results to various test systems. One major idea of our work is adopting the open standards approach to guarantee interoperability. In addition, modeling methodologies for virtual tester and virtual silicon are proposed to further enhance interoperability between virtual and real test. To give an insight on how such environment seamlessly integrates into the test development flow, an ADC test which is performed both on the virtual platform and the real tester is described. The simulation environment is built using SystemC/-AMS libraries. © 2009 IEEE.
UnivIS-Import:2015-04-16:Pub.2009.tech.IE.c3scha.mixeds

Optimales, skalierbares Ressourcenmanagement für modulare, gemischt analog-digitale Testsysteme - Uygur, Gürkan; Lu, Ping; Glaser, Daniel; Weichselgartner, Susanne; Helmreich, Klaus; Sattler, Sebastian; Lechner, Armin; Brenneke, Andreas (Tagungsband, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IE.c3scha.optima

Standardized Characterisation of Device Power Supplies for Automated Test Generation and Simulation - Glaser, Daniel; Müller, Andreas; Lu, Ping; Uygur, Gürkan; Helmreich, Klaus (Tagungsband, 2010)
UnivIS-Import:2015-04-16:Pub.2010.tech.IE.c3scha.standa_5

Standards-Based Construction of a Virtual Test Environment - Lu, Ping; Helmreich, Klaus (Tagungsband, 2008)
UnivIS-Import:2015-04-16:Pub.2008.tech.IE.c3scha.standa

The Best of Both Worlds: Merging the Benefits of Rack&Stack and Universal ATE - Lu, Ping; Glaser, Daniel; Uygur, Gürkan; Helmreich, Klaus (Conference Proceedings, 2009)
Test cost is and will continue to be one of the most important issues, especially in testing analog, mixed-signal and RF devices. When considering overall test cost, the key factors are low cost test equipment, low cost of ownership and low test development cost. Universal ATE ('big iron') is associated with high equipment cost but its powerful SW enables cost-efficient test development. Rack&Stack systems, on the other hand, can be assembled from inexpensive components, but load test engineers with much higher effort for test development and debug. This paper describes a concept that promises to combine the respective advantages of Rack&Stack and universal test systems by establishing a versatile test platform in HW based on industry standards enabling modular, least-cost, application-specific configuration with a likewise standard based SW environment for efficient test generation and debug, inherently supporting virtual test and test synthesis from formal specification. © 2009 IEEE.
UnivIS-Import:2015-04-16:Pub.2009.tech.IE.c3scha.thebes

Vollständige Integration des virtuellen Tests in den Entwurfsprozess integrierter Schaltungen - Glaser, Daniel; Lu, Ping; Helmreich, Klaus (Tagungsband, 2009)
UnivIS-Import:2015-04-16:Pub.2009.tech.IE.c3scha.vollst